Lines Matching refs:gs

273 	struct tegra_hte_soc *gs;  in tegra_hte_line_xlate()  local
290 gs = gc->data; in tegra_hte_line_xlate()
291 if (!gs || !gs->prov_data) in tegra_hte_line_xlate()
305 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && !args) { in tegra_hte_line_xlate()
306 line_id = desc->attr.line_id - gs->c->base; in tegra_hte_line_xlate()
307 map = gs->prov_data->map; in tegra_hte_line_xlate()
308 map_sz = gs->prov_data->map_sz; in tegra_hte_line_xlate()
309 } else if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && args) { in tegra_hte_line_xlate()
311 map = gs->prov_data->sec_map; in tegra_hte_line_xlate()
312 map_sz = gs->prov_data->sec_map_sz; in tegra_hte_line_xlate()
342 struct tegra_hte_soc *gs; in tegra_hte_en_dis_common() local
349 gs = chip->data; in tegra_hte_en_dis_common()
362 spin_lock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
364 if (test_bit(HTE_SUSPEND, &gs->sl[slice].flags)) { in tegra_hte_en_dis_common()
365 spin_unlock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
370 val = tegra_hte_readl(gs, reg); in tegra_hte_en_dis_common()
375 tegra_hte_writel(gs, reg, val); in tegra_hte_en_dis_common()
377 spin_unlock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
405 struct tegra_hte_soc *gs; in tegra_hte_request() local
411 gs = chip->data; in tegra_hte_request()
414 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_request()
423 gs->line_data[line_id].data = attr->line_data; in tegra_hte_request()
424 gs->line_data[line_id].flags = attr->edge_flags; in tegra_hte_request()
433 struct tegra_hte_soc *gs; in tegra_hte_release() local
440 gs = chip->data; in tegra_hte_release()
443 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_release()
445 gs->line_data[line_id].flags); in tegra_hte_release()
449 gs->line_data[line_id].data = NULL; in tegra_hte_release()
450 gs->line_data[line_id].flags = 0; in tegra_hte_release()
470 static int tegra_hte_get_level(struct tegra_hte_soc *gs, u32 line_id) in tegra_hte_get_level() argument
474 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { in tegra_hte_get_level()
475 desc = gs->line_data[line_id].data; in tegra_hte_get_level()
483 static void tegra_hte_read_fifo(struct tegra_hte_soc *gs) in tegra_hte_read_fifo() argument
489 while ((tegra_hte_readl(gs, HTE_TESTATUS) >> in tegra_hte_read_fifo()
492 tsh = tegra_hte_readl(gs, HTE_TETSCH); in tegra_hte_read_fifo()
493 tsl = tegra_hte_readl(gs, HTE_TETSCL); in tegra_hte_read_fifo()
496 src = tegra_hte_readl(gs, HTE_TESRC); in tegra_hte_read_fifo()
500 pv = tegra_hte_readl(gs, HTE_TEPCV); in tegra_hte_read_fifo()
501 cv = tegra_hte_readl(gs, HTE_TECCV); in tegra_hte_read_fifo()
507 el.raw_level = tegra_hte_get_level(gs, line_id); in tegra_hte_read_fifo()
508 hte_push_ts_ns(gs->chip, line_id, &el); in tegra_hte_read_fifo()
511 tegra_hte_writel(gs, HTE_TECMD, HTE_TECMD_CMD_POP); in tegra_hte_read_fifo()
517 struct tegra_hte_soc *gs = dev_id; in tegra_hte_isr() local
520 tegra_hte_read_fifo(gs); in tegra_hte_isr()
554 struct tegra_hte_soc *gs = dev_get_drvdata(&pdev->dev); in tegra_gte_disable() local
556 tegra_hte_writel(gs, HTE_TECTRL, 0); in tegra_gte_disable()
675 struct tegra_hte_soc *gs = dev_get_drvdata(dev); in tegra_hte_resume_early() local
676 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; in tegra_hte_resume_early()
679 tegra_hte_writel(gs, HTE_TECTRL, gs->conf_rval); in tegra_hte_resume_early()
682 spin_lock(&gs->sl[i].s_lock); in tegra_hte_resume_early()
683 tegra_hte_writel(gs, in tegra_hte_resume_early()
685 gs->sl[i].r_val); in tegra_hte_resume_early()
686 clear_bit(HTE_SUSPEND, &gs->sl[i].flags); in tegra_hte_resume_early()
687 spin_unlock(&gs->sl[i].s_lock); in tegra_hte_resume_early()
696 struct tegra_hte_soc *gs = dev_get_drvdata(dev); in tegra_hte_suspend_late() local
697 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; in tegra_hte_suspend_late()
700 gs->conf_rval = tegra_hte_readl(gs, HTE_TECTRL); in tegra_hte_suspend_late()
702 spin_lock(&gs->sl[i].s_lock); in tegra_hte_suspend_late()
703 gs->sl[i].r_val = tegra_hte_readl(gs, in tegra_hte_suspend_late()
705 set_bit(HTE_SUSPEND, &gs->sl[i].flags); in tegra_hte_suspend_late()
706 spin_unlock(&gs->sl[i].s_lock); in tegra_hte_suspend_late()