Lines Matching refs:IPU_CM_REG

30 #define IPU_CM_REG(offset)	(offset)  macro
32 #define IPU_CONF			IPU_CM_REG(0)
34 #define IPU_SRM_PRI1			IPU_CM_REG(0x00a0)
35 #define IPU_SRM_PRI2			IPU_CM_REG(0x00a4)
36 #define IPU_FS_PROC_FLOW1		IPU_CM_REG(0x00a8)
37 #define IPU_FS_PROC_FLOW2		IPU_CM_REG(0x00ac)
38 #define IPU_FS_PROC_FLOW3		IPU_CM_REG(0x00b0)
39 #define IPU_FS_DISP_FLOW1		IPU_CM_REG(0x00b4)
40 #define IPU_FS_DISP_FLOW2		IPU_CM_REG(0x00b8)
41 #define IPU_SKIP			IPU_CM_REG(0x00bc)
42 #define IPU_DISP_ALT_CONF		IPU_CM_REG(0x00c0)
43 #define IPU_DISP_GEN			IPU_CM_REG(0x00c4)
44 #define IPU_DISP_ALT1			IPU_CM_REG(0x00c8)
45 #define IPU_DISP_ALT2			IPU_CM_REG(0x00cc)
46 #define IPU_DISP_ALT3			IPU_CM_REG(0x00d0)
47 #define IPU_DISP_ALT4			IPU_CM_REG(0x00d4)
48 #define IPU_SNOOP			IPU_CM_REG(0x00d8)
49 #define IPU_MEM_RST			IPU_CM_REG(0x00dc)
50 #define IPU_PM				IPU_CM_REG(0x00e0)
51 #define IPU_GPR				IPU_CM_REG(0x00e4)
52 #define IPU_CHA_DB_MODE_SEL(ch)		IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
53 #define IPU_ALT_CHA_DB_MODE_SEL(ch)	IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
54 #define IPU_CHA_CUR_BUF(ch)		IPU_CM_REG(0x023C + 4 * ((ch) / 32))
55 #define IPU_ALT_CUR_BUF0		IPU_CM_REG(0x0244)
56 #define IPU_ALT_CUR_BUF1		IPU_CM_REG(0x0248)
57 #define IPU_SRM_STAT			IPU_CM_REG(0x024C)
58 #define IPU_PROC_TASK_STAT		IPU_CM_REG(0x0250)
59 #define IPU_DISP_TASK_STAT		IPU_CM_REG(0x0254)
60 #define IPU_CHA_BUF0_RDY(ch)		IPU_CM_REG(0x0268 + 4 * ((ch) / 32))
61 #define IPU_CHA_BUF1_RDY(ch)		IPU_CM_REG(0x0270 + 4 * ((ch) / 32))
62 #define IPU_CHA_BUF2_RDY(ch)		IPU_CM_REG(0x0288 + 4 * ((ch) / 32))
63 #define IPU_ALT_CHA_BUF0_RDY(ch)	IPU_CM_REG(0x0278 + 4 * ((ch) / 32))
64 #define IPU_ALT_CHA_BUF1_RDY(ch)	IPU_CM_REG(0x0280 + 4 * ((ch) / 32))
66 #define IPU_INT_CTRL(n)		IPU_CM_REG(0x003C + 4 * (n))
67 #define IPU_INT_STAT(n)		IPU_CM_REG(0x0200 + 4 * (n))