387 	const u8 *lane_map;  member
655 		value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |  in tegra_sor_power_up_lanes()
656 			   SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));  in tegra_sor_power_up_lanes()
658 		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |  in tegra_sor_power_up_lanes()
659 			 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);  in tegra_sor_power_up_lanes()
662 		value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);  in tegra_sor_power_up_lanes()
664 		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);  in tegra_sor_power_up_lanes()
667 		value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);  in tegra_sor_power_up_lanes()
669 		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);  in tegra_sor_power_up_lanes()
734 		value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |  in tegra_sor_dp_precharge()
735 			   SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));  in tegra_sor_dp_precharge()
737 		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |  in tegra_sor_dp_precharge()
738 			 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);  in tegra_sor_dp_precharge()
741 		value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);  in tegra_sor_dp_precharge()
743 		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);  in tegra_sor_dp_precharge()
746 		value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);  in tegra_sor_dp_precharge()
748 		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);  in tegra_sor_dp_precharge()
813 		u8 shift = sor->soc->lane_map[i] << 3;  in tegra_sor_dp_link_apply_training()
3409 	.lane_map = tegra124_sor_lane_map,
3449 	.lane_map = tegra124_sor_lane_map,
3490 	.lane_map = tegra210_sor_lane_map,
3510 	.lane_map = tegra210_sor_lane_map,
3593 	.lane_map = tegra124_sor_lane_map,
3629 	.lane_map = tegra124_sor_lane_map,