3508 					   struct radeon_ps *new_ps,  in ni_set_uvd_clock_before_set_eng_clock()  argument
3511 	struct ni_ps *new_state = ni_get_ps(new_ps);  in ni_set_uvd_clock_before_set_eng_clock()
3514 	if ((new_ps->vclk == old_ps->vclk) &&  in ni_set_uvd_clock_before_set_eng_clock()
3515 	    (new_ps->dclk == old_ps->dclk))  in ni_set_uvd_clock_before_set_eng_clock()
3522 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_before_set_eng_clock()
3526 					  struct radeon_ps *new_ps,  in ni_set_uvd_clock_after_set_eng_clock()  argument
3529 	struct ni_ps *new_state = ni_get_ps(new_ps);  in ni_set_uvd_clock_after_set_eng_clock()
3532 	if ((new_ps->vclk == old_ps->vclk) &&  in ni_set_uvd_clock_after_set_eng_clock()
3533 	    (new_ps->dclk == old_ps->dclk))  in ni_set_uvd_clock_after_set_eng_clock()
3540 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_after_set_eng_clock()
3563 	struct ni_ps *new_ps = ni_get_ps(rps);  in ni_update_current_ps()  local
3568 	ni_pi->current_ps = *new_ps;  in ni_update_current_ps()
3575 	struct ni_ps *new_ps = ni_get_ps(rps);  in ni_update_requested_ps()  local
3580 	ni_pi->requested_ps = *new_ps;  in ni_update_requested_ps()
3742 	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;  in ni_power_control_set_level()  local
3751 	ret = ni_populate_smc_tdp_limits(rdev, new_ps);  in ni_power_control_set_level()
3768 	struct radeon_ps *new_ps = &requested_ps;  in ni_dpm_pre_set_power_state()  local
3770 	ni_update_requested_ps(rdev, new_ps);  in ni_dpm_pre_set_power_state()
3780 	struct radeon_ps *new_ps = &eg_pi->requested_rps;  in ni_dpm_set_power_state()  local
3789 	ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);  in ni_dpm_set_power_state()
3790 	ret = ni_enable_power_containment(rdev, new_ps, false);  in ni_dpm_set_power_state()
3795 	ret = ni_enable_smc_cac(rdev, new_ps, false);  in ni_dpm_set_power_state()
3806 		btc_notify_uvd_to_smc(rdev, new_ps);  in ni_dpm_set_power_state()
3807 	ret = ni_upload_sw_state(rdev, new_ps);  in ni_dpm_set_power_state()
3813 		ret = ni_upload_mc_reg_table(rdev, new_ps);  in ni_dpm_set_power_state()
3819 	ret = ni_program_memory_timing_parameters(rdev, new_ps);  in ni_dpm_set_power_state()
3834 	ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);  in ni_dpm_set_power_state()
3835 	ret = ni_enable_smc_cac(rdev, new_ps, true);  in ni_dpm_set_power_state()
3840 	ret = ni_enable_power_containment(rdev, new_ps, true);  in ni_dpm_set_power_state()
3859 	struct radeon_ps *new_ps = &eg_pi->requested_rps;  in ni_dpm_post_set_power_state()  local
3861 	ni_update_current_ps(rdev, new_ps);  in ni_dpm_post_set_power_state()