Lines Matching refs:mc_reg_table
833 for (i = 0; i < eg_pi->mc_reg_table.num_entries; i++) { in cypress_convert_mc_reg_table_entry_to_smc()
835 eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in cypress_convert_mc_reg_table_entry_to_smc()
839 if ((i == eg_pi->mc_reg_table.num_entries) && (i > 0)) in cypress_convert_mc_reg_table_entry_to_smc()
842 cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[i], in cypress_convert_mc_reg_table_entry_to_smc()
844 eg_pi->mc_reg_table.last, in cypress_convert_mc_reg_table_entry_to_smc()
845 eg_pi->mc_reg_table.valid_flag); in cypress_convert_mc_reg_table_entry_to_smc()
850 SMC_Evergreen_MCRegisters *mc_reg_table) in cypress_convert_mc_reg_table_to_smc() argument
856 &mc_reg_table->data[2]); in cypress_convert_mc_reg_table_to_smc()
859 &mc_reg_table->data[3]); in cypress_convert_mc_reg_table_to_smc()
862 &mc_reg_table->data[4]); in cypress_convert_mc_reg_table_to_smc()
888 SMC_Evergreen_MCRegisters mc_reg_table = { 0 }; in cypress_upload_mc_reg_table() local
891 cypress_convert_mc_reg_table_to_smc(rdev, radeon_new_state, &mc_reg_table); in cypress_upload_mc_reg_table()
897 (u8 *)&mc_reg_table.data[2], in cypress_upload_mc_reg_table()
947 SMC_Evergreen_MCRegisters *mc_reg_table) in cypress_populate_mc_reg_addresses() argument
952 for (i = 0, j = 0; j < eg_pi->mc_reg_table.last; j++) { in cypress_populate_mc_reg_addresses()
953 if (eg_pi->mc_reg_table.valid_flag & (1 << j)) { in cypress_populate_mc_reg_addresses()
954 mc_reg_table->address[i].s0 = in cypress_populate_mc_reg_addresses()
955 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0); in cypress_populate_mc_reg_addresses()
956 mc_reg_table->address[i].s1 = in cypress_populate_mc_reg_addresses()
957 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1); in cypress_populate_mc_reg_addresses()
962 mc_reg_table->last = (u8)i; in cypress_populate_mc_reg_addresses()
970 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()
971 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2; in cypress_set_mc_reg_address_table()
974 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()
975 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2; in cypress_set_mc_reg_address_table()
978 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()
979 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2; in cypress_set_mc_reg_address_table()
982 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2; in cypress_set_mc_reg_address_table()
983 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2; in cypress_set_mc_reg_address_table()
986 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2; in cypress_set_mc_reg_address_table()
987 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2; in cypress_set_mc_reg_address_table()
990 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2; in cypress_set_mc_reg_address_table()
991 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2; in cypress_set_mc_reg_address_table()
994 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2; in cypress_set_mc_reg_address_table()
995 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2; in cypress_set_mc_reg_address_table()
998 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2; in cypress_set_mc_reg_address_table()
999 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2; in cypress_set_mc_reg_address_table()
1002 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in cypress_set_mc_reg_address_table()
1003 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2; in cypress_set_mc_reg_address_table()
1006 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in cypress_set_mc_reg_address_table()
1007 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2; in cypress_set_mc_reg_address_table()
1010 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in cypress_set_mc_reg_address_table()
1011 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2; in cypress_set_mc_reg_address_table()
1014 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2; in cypress_set_mc_reg_address_table()
1015 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2; in cypress_set_mc_reg_address_table()
1018 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2; in cypress_set_mc_reg_address_table()
1019 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2; in cypress_set_mc_reg_address_table()
1022 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2; in cypress_set_mc_reg_address_table()
1023 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2; in cypress_set_mc_reg_address_table()
1026 eg_pi->mc_reg_table.last = (u8)i; in cypress_set_mc_reg_address_table()
1035 for (i = 0; i < eg_pi->mc_reg_table.last; i++) in cypress_retrieve_ac_timing_for_one_entry()
1037 RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); in cypress_retrieve_ac_timing_for_one_entry()
1048 eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max = in cypress_retrieve_ac_timing_for_all_ranges()
1052 &eg_pi->mc_reg_table.mc_reg_table_entry[i]); in cypress_retrieve_ac_timing_for_all_ranges()
1055 eg_pi->mc_reg_table.num_entries = range_table->num_entries; in cypress_retrieve_ac_timing_for_all_ranges()
1056 eg_pi->mc_reg_table.valid_flag = 0; in cypress_retrieve_ac_timing_for_all_ranges()
1058 for (i = 0; i < eg_pi->mc_reg_table.last; i++) { in cypress_retrieve_ac_timing_for_all_ranges()
1060 if (eg_pi->mc_reg_table.mc_reg_table_entry[j-1].mc_data[i] != in cypress_retrieve_ac_timing_for_all_ranges()
1061 eg_pi->mc_reg_table.mc_reg_table_entry[j].mc_data[i]) { in cypress_retrieve_ac_timing_for_all_ranges()
1062 eg_pi->mc_reg_table.valid_flag |= (1 << i); in cypress_retrieve_ac_timing_for_all_ranges()
1170 for (i = 0; i < eg_pi->mc_reg_table.last; i++) { in cypress_copy_ac_timing_from_s1_to_s0()
1171 value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); in cypress_copy_ac_timing_from_s1_to_s0()
1172 WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value); in cypress_copy_ac_timing_from_s1_to_s0()
1668 SMC_Evergreen_MCRegisters mc_reg_table = { 0 }; in cypress_populate_mc_reg_table() local
1673 cypress_populate_mc_reg_addresses(rdev, &mc_reg_table); in cypress_populate_mc_reg_table()
1677 &mc_reg_table.data[0]); in cypress_populate_mc_reg_table()
1679 cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[0], in cypress_populate_mc_reg_table()
1680 &mc_reg_table.data[1], eg_pi->mc_reg_table.last, in cypress_populate_mc_reg_table()
1681 eg_pi->mc_reg_table.valid_flag); in cypress_populate_mc_reg_table()
1683 cypress_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, &mc_reg_table); in cypress_populate_mc_reg_table()
1686 (u8 *)&mc_reg_table, sizeof(SMC_Evergreen_MCRegisters), in cypress_populate_mc_reg_table()