Lines Matching refs:performance_level_count
805 for (i = 0; i < ps->performance_level_count; i++) { in ci_apply_state_adjust_rules()
816 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in ci_apply_state_adjust_rules()
3719 if (state->performance_level_count < 1) in ci_trim_dpm_states()
3722 if (state->performance_level_count == 1) in ci_trim_dpm_states()
3824 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_find_dpm_states_clocks_in_dpm_table()
3826 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_find_dpm_states_clocks_in_dpm_table()
3865 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3866 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
4767 for (i = 0; i < state->performance_level_count; i++) { in ci_get_maximum_link_speed()
5445 ps->performance_level_count = index + 1; in ci_parse_pplib_clock_info()
5928 for (i = 0; i < ps->performance_level_count; i++) { in ci_dpm_print_power_state()
5958 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; in ci_dpm_get_sclk()
5969 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; in ci_dpm_get_mclk()