Lines Matching refs:define
25 #define GT215 0xa3
26 #define GF100 0xc0
27 #define GF119 0xd9
28 #define GK208 0x108
33 #define NV_PPWR_INTR_TRIGGER 0x0000
34 #define NV_PPWR_INTR_TRIGGER_USER1 0x00000080
35 #define NV_PPWR_INTR_TRIGGER_USER0 0x00000040
36 #define NV_PPWR_INTR_ACK 0x0004
37 #define NV_PPWR_INTR_ACK_SUBINTR 0x00000800
38 #define NV_PPWR_INTR_ACK_WATCHDOG 0x00000002
39 #define NV_PPWR_INTR 0x0008
40 #define NV_PPWR_INTR_SUBINTR 0x00000800
41 #define NV_PPWR_INTR_USER1 0x00000080
42 #define NV_PPWR_INTR_USER0 0x00000040
43 #define NV_PPWR_INTR_PAUSE 0x00000020
44 #define NV_PPWR_INTR_WATCHDOG 0x00000002
45 #define NV_PPWR_INTR_EN_SET 0x0010
46 #define NV_PPWR_INTR_EN_SET_SUBINTR 0x00000800
47 #define NV_PPWR_INTR_EN_SET_WATCHDOG 0x00000002
48 #define NV_PPWR_INTR_EN_CLR 0x0014
49 #define NV_PPWR_INTR_EN_CLR_MASK /* fuck i hate envyas */ -1
50 #define NV_PPWR_INTR_ROUTE 0x001c
51 #define NV_PPWR_TIMER_LOW 0x002c
52 #define NV_PPWR_WATCHDOG_TIME 0x0034
53 #define NV_PPWR_WATCHDOG_ENABLE 0x0038
54 #define NV_PPWR_CAPS 0x0108
55 #define NV_PPWR_UAS_CONFIG 0x0164
56 #define NV_PPWR_UAS_CONFIG_ENABLE 0x00010000
58 #define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x0450)
60 #define NV_PPWR_FIFO_PUT(i) (4 * (i) + 0x04a0)
61 #define NV_PPWR_FIFO_GET(i) (4 * (i) + 0x04b0)
62 #define NV_PPWR_FIFO_INTR 0x04c0
63 #define NV_PPWR_FIFO_INTR_EN 0x04c4
64 #define NV_PPWR_RFIFO_PUT 0x04c8
65 #define NV_PPWR_RFIFO_GET 0x04cc
66 #define NV_PPWR_H2D 0x04d0
67 #define NV_PPWR_D2H 0x04dc
69 #define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x05d0)
71 #define NV_PPWR_SUBINTR 0x0688
72 #define NV_PPWR_SUBINTR_FIFO 0x00000002
73 #define NV_PPWR_MMIO_ADDR 0x07a0
74 #define NV_PPWR_MMIO_DATA 0x07a4
75 #define NV_PPWR_MMIO_CTRL 0x07ac
76 #define NV_PPWR_MMIO_CTRL_TRIGGER 0x00010000
77 #define NV_PPWR_MMIO_CTRL_STATUS 0x00007000
78 #define NV_PPWR_MMIO_CTRL_STATUS_IDLE 0x00000000
79 #define NV_PPWR_MMIO_CTRL_MASK 0x000000f0
80 #define NV_PPWR_MMIO_CTRL_MASK_B32_0 0x000000f0
81 #define NV_PPWR_MMIO_CTRL_OP 0x00000003
82 #define NV_PPWR_MMIO_CTRL_OP_RD 0x00000001
83 #define NV_PPWR_MMIO_CTRL_OP_WR 0x00000002
84 #define NV_PPWR_OUTPUT 0x07c0
85 #define NV_PPWR_OUTPUT_FB_PAUSE 0x00000004
87 #define NV_PPWR_OUTPUT_I2C_3_SCL 0x00000100
88 #define NV_PPWR_OUTPUT_I2C_3_SDA 0x00000200
89 #define NV_PPWR_OUTPUT_I2C_0_SCL 0x00001000
90 #define NV_PPWR_OUTPUT_I2C_0_SDA 0x00002000
91 #define NV_PPWR_OUTPUT_I2C_1_SCL 0x00004000
92 #define NV_PPWR_OUTPUT_I2C_1_SDA 0x00008000
93 #define NV_PPWR_OUTPUT_I2C_2_SCL 0x00010000
94 #define NV_PPWR_OUTPUT_I2C_2_SDA 0x00020000
95 #define NV_PPWR_OUTPUT_I2C_4_SCL 0x00040000
96 #define NV_PPWR_OUTPUT_I2C_4_SDA 0x00080000
97 #define NV_PPWR_OUTPUT_I2C_5_SCL 0x00100000
98 #define NV_PPWR_OUTPUT_I2C_5_SDA 0x00200000
99 #define NV_PPWR_OUTPUT_I2C_6_SCL 0x00400000
100 #define NV_PPWR_OUTPUT_I2C_6_SDA 0x00800000
101 #define NV_PPWR_OUTPUT_I2C_7_SCL 0x01000000
102 #define NV_PPWR_OUTPUT_I2C_7_SDA 0x02000000
103 #define NV_PPWR_OUTPUT_I2C_8_SCL 0x04000000
104 #define NV_PPWR_OUTPUT_I2C_8_SDA 0x08000000
105 #define NV_PPWR_OUTPUT_I2C_9_SCL 0x10000000
106 #define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000
108 #define NV_PPWR_OUTPUT_I2C_0_SCL 0x00000400
109 #define NV_PPWR_OUTPUT_I2C_1_SCL 0x00000800
110 #define NV_PPWR_OUTPUT_I2C_2_SCL 0x00001000
111 #define NV_PPWR_OUTPUT_I2C_3_SCL 0x00002000
112 #define NV_PPWR_OUTPUT_I2C_4_SCL 0x00004000
113 #define NV_PPWR_OUTPUT_I2C_5_SCL 0x00008000
114 #define NV_PPWR_OUTPUT_I2C_6_SCL 0x00010000
115 #define NV_PPWR_OUTPUT_I2C_7_SCL 0x00020000
116 #define NV_PPWR_OUTPUT_I2C_8_SCL 0x00040000
117 #define NV_PPWR_OUTPUT_I2C_9_SCL 0x00080000
118 #define NV_PPWR_OUTPUT_I2C_0_SDA 0x00100000
119 #define NV_PPWR_OUTPUT_I2C_1_SDA 0x00200000
120 #define NV_PPWR_OUTPUT_I2C_2_SDA 0x00400000
121 #define NV_PPWR_OUTPUT_I2C_3_SDA 0x00800000
122 #define NV_PPWR_OUTPUT_I2C_4_SDA 0x01000000
123 #define NV_PPWR_OUTPUT_I2C_5_SDA 0x02000000
124 #define NV_PPWR_OUTPUT_I2C_6_SDA 0x04000000
125 #define NV_PPWR_OUTPUT_I2C_7_SDA 0x08000000
126 #define NV_PPWR_OUTPUT_I2C_8_SDA 0x10000000
127 #define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000
129 #define NV_PPWR_INPUT 0x07c4
130 #define NV_PPWR_OUTPUT_SET 0x07e0
131 #define NV_PPWR_OUTPUT_SET_FB_PAUSE 0x00000004
132 #define NV_PPWR_OUTPUT_CLR 0x07e4
133 #define NV_PPWR_OUTPUT_CLR_FB_PAUSE 0x00000004
142 #define KMSG_FIFO 0x00000000
143 #define KMSG_ALARM 0x00000001
163 #define process(id,init,recv) /*
173 #define imm32(reg,val) /*
177 #define imm32(reg,val) /*
182 #define nv_iord(reg,ior) /*
187 #define nv_iord(reg,ior) /*
193 #define nv_iowr(ior,reg) /*
199 #define nv_iowr(ior,reg) /*
206 #define nv_iowrs(ior,reg) /*
212 #define nv_iowrs(ior,reg) /*
218 #define hash #
219 #define fn(a) a
221 #define call(a) call fn(hash)a
223 #define call(a) lcall fn(hash)a
227 #define nv_rd32(reg,addr) /*
232 #define nv_rd32(reg,addr) /*
240 #define nv_wr32(addr,reg) /*
247 #define nv_wr32(addr,reg) /*
254 #define st(size, addr, reg) /*
259 #define ld(size, reg, addr) /*
265 #define addu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /*
270 #define subu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /*