73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing)  in nv50_ram_timing_calc()  argument
98 		timing[6] = (0x2d + T(CL) - T(CWL) +  in nv50_ram_timing_calc()
104 		timing[6] = (0x2b + T(CL) - T(CWL)) << 16 |  in nv50_ram_timing_calc()
109 	timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));  in nv50_ram_timing_calc()
110 	timing[1] = (T(WR) + 1 + T(CWL)) << 24 |  in nv50_ram_timing_calc()
114 	timing[2] = (T(CWL) - 1) << 24 |  in nv50_ram_timing_calc()
118 	timing[3] = (unkt3b - 2 + T(CL)) << 24 |  in nv50_ram_timing_calc()
122 	timing[4] = (cur4 & 0xffff0000) |  in nv50_ram_timing_calc()
125 	timing[5] = T(RFC) << 24 |  in nv50_ram_timing_calc()
129 	timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16;  in nv50_ram_timing_calc()
130 	timing[8] = (cur8 & 0xffffff00);  in nv50_ram_timing_calc()
134 		timing[5] |= (T(CL) + 3) << 8;  in nv50_ram_timing_calc()
135 		timing[8] |= (T(CL) - 4);  in nv50_ram_timing_calc()
138 		timing[5] |= (T(CL) + 2) << 8;  in nv50_ram_timing_calc()
139 		timing[8] |= (T(CL) - 2);  in nv50_ram_timing_calc()
143 		   timing[0], timing[1], timing[2], timing[3]);  in nv50_ram_timing_calc()
145 		   timing[4], timing[5], timing[6], timing[7]);  in nv50_ram_timing_calc()
146 	nvkm_debug(subdev, " 240: %08x\n", timing[8]);  in nv50_ram_timing_calc()
151 nv50_ram_timing_read(struct nv50_ram *ram, u32 *timing)  in nv50_ram_timing_read()  argument
159 		timing[i] = nvkm_rd32(device, 0x100220 + (i * 4));  in nv50_ram_timing_read()
163 	T(CL) = (timing[3] & 0xff) + 1;  in nv50_ram_timing_read()
170 		T(CWL) = ((timing[2] & 0xff000000) >> 24) + 1;  in nv50_ram_timing_read()
176 	T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL);  in nv50_ram_timing_read()
232 	u32 timing[9];  in nv50_ram_calc()  local
276 		nv50_ram_timing_calc(ram, timing);  in nv50_ram_calc()
278 		nv50_ram_timing_read(ram, timing);  in nv50_ram_calc()
389 	ram_mask(hwsq, timing[3], 0xffffffff, timing[3]);  in nv50_ram_calc()
390 	ram_mask(hwsq, timing[1], 0xffffffff, timing[1]);  in nv50_ram_calc()
391 	ram_mask(hwsq, timing[6], 0xffffffff, timing[6]);  in nv50_ram_calc()
392 	ram_mask(hwsq, timing[7], 0xffffffff, timing[7]);  in nv50_ram_calc()
393 	ram_mask(hwsq, timing[8], 0xffffffff, timing[8]);  in nv50_ram_calc()
394 	ram_mask(hwsq, timing[0], 0xffffffff, timing[0]);  in nv50_ram_calc()
395 	ram_mask(hwsq, timing[2], 0xffffffff, timing[2]);  in nv50_ram_calc()
396 	ram_mask(hwsq, timing[4], 0xffffffff, timing[4]);  in nv50_ram_calc()
397 	ram_mask(hwsq, timing[5], 0xffffffff, timing[5]);  in nv50_ram_calc()