159 		nvkm_wr32(device, 0x001584,  in setPLL_single()
166 		nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff));  in setPLL_single()
169 		nvkm_wr32(device, reg, (oldpll & 0xffff0000) | pv->NM1);  in setPLL_single()
178 	nvkm_wr32(device, reg, pll);  in setPLL_single()
181 		nvkm_wr32(device, 0x001584, saved_powerctrl_1);  in setPLL_single()
238 		nvkm_wr32(device, 0x001584,  in setPLL_double_highregs()
259 			nvkm_wr32(device, 0xc040, savedc040 & ~(3 << shift_c040));  in setPLL_double_highregs()
263 		nvkm_wr32(device, 0x680580, ramdac580);  in setPLL_double_highregs()
266 		nvkm_wr32(device, reg2, pll2);  in setPLL_double_highregs()
267 	nvkm_wr32(device, reg1, pll1);  in setPLL_double_highregs()
270 		nvkm_wr32(device, 0x001584, saved_powerctrl_1);  in setPLL_double_highregs()
272 		nvkm_wr32(device, 0xc040, savedc040);  in setPLL_double_highregs()
319 		nvkm_wr32(device, 0x4600, saved4600 | 8 << 28);  in setPLL_double_lowregs()
324 	nvkm_wr32(device, Preg, oldPval | 1 << 28);  in setPLL_double_lowregs()
325 	nvkm_wr32(device, Preg, Pval & ~(4 << 28));  in setPLL_double_lowregs()
328 		nvkm_wr32(device, 0x4020, Pval & ~(0xc << 28));  in setPLL_double_lowregs()
329 		nvkm_wr32(device, 0x4038, Pval & ~(0xc << 28));  in setPLL_double_lowregs()
333 	nvkm_wr32(device, 0xc040, savedc040 & maskc040);  in setPLL_double_lowregs()
335 	nvkm_wr32(device, NMNMreg, NMNM);  in setPLL_double_lowregs()
337 		nvkm_wr32(device, 0x403c, NMNM);  in setPLL_double_lowregs()
339 	nvkm_wr32(device, Preg, Pval);  in setPLL_double_lowregs()
342 		nvkm_wr32(device, 0x4020, Pval);  in setPLL_double_lowregs()
343 		nvkm_wr32(device, 0x4038, Pval);  in setPLL_double_lowregs()
344 		nvkm_wr32(device, 0x4600, saved4600);  in setPLL_double_lowregs()
347 	nvkm_wr32(device, 0xc040, savedc040);  in setPLL_double_lowregs()
350 		nvkm_wr32(device, 0x4020, Pval & ~(1 << 28));  in setPLL_double_lowregs()
351 		nvkm_wr32(device, 0x4038, Pval & ~(1 << 28));  in setPLL_double_lowregs()