36 	return nvkm_rd32(gr->engine.subdev.device, 0x1540);  in nv40_gr_units()
103 	if (nvkm_rd32(device, 0x40032c) == inst) {  in nv40_gr_chan_fini()
110 				if (!(nvkm_rd32(device, 0x400300) & 0x00000001))  in nv40_gr_chan_fini()
113 				u32 insn = nvkm_rd32(device, 0x400308);  in nv40_gr_chan_fini()
122 	if (nvkm_rd32(device, 0x400330) == inst)  in nv40_gr_chan_fini()
238 	u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);  in nv40_gr_intr()
239 	u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);  in nv40_gr_intr()
240 	u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);  in nv40_gr_intr()
241 	u32 inst = nvkm_rd32(device, 0x40032c) & 0x000fffff;  in nv40_gr_intr()
242 	u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);  in nv40_gr_intr()
245 	u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);  in nv40_gr_intr()
246 	u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff;  in nv40_gr_intr()
315 	j = nvkm_rd32(device, 0x1540) & 0xff;  in nv40_gr_init()
392 		nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));  in nv40_gr_init()
393 		nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));  in nv40_gr_init()
394 		nvkm_wr32(device, 0x4069A4, nvkm_rd32(device, 0x100200));  in nv40_gr_init()
395 		nvkm_wr32(device, 0x4069A8, nvkm_rd32(device, 0x100204));  in nv40_gr_init()
410 			nvkm_wr32(device, 0x4009F0, nvkm_rd32(device, 0x100200));  in nv40_gr_init()
411 			nvkm_wr32(device, 0x4009F4, nvkm_rd32(device, 0x100204));  in nv40_gr_init()
414 			nvkm_wr32(device, 0x400DF0, nvkm_rd32(device, 0x100200));  in nv40_gr_init()
415 			nvkm_wr32(device, 0x400DF4, nvkm_rd32(device, 0x100204));  in nv40_gr_init()
418 		nvkm_wr32(device, 0x4069F0, nvkm_rd32(device, 0x100200));  in nv40_gr_init()
419 		nvkm_wr32(device, 0x4069F4, nvkm_rd32(device, 0x100204));  in nv40_gr_init()