417 		nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr);		\
425 		nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr);		\
427 			nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, state[__i]); \
464 	nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000);  in nv17_gr_mthd_lma_window()
465 	nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000);  in nv17_gr_mthd_lma_window()
466 	nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);  in nv17_gr_mthd_lma_window()
468 		nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000);  in nv17_gr_mthd_lma_window()
470 		nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);  in nv17_gr_mthd_lma_window()
472 	nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);  in nv17_gr_mthd_lma_window()
474 		nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000);  in nv17_gr_mthd_lma_window()
476 	nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);  in nv17_gr_mthd_lma_window()
478 		nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);  in nv17_gr_mthd_lma_window()
480 	nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);  in nv17_gr_mthd_lma_window()
481 	nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000008);  in nv17_gr_mthd_lma_window()
489 	nvkm_wr32(device, NV10_PGRAPH_XFMODE0, xfmode0);  in nv17_gr_mthd_lma_window()
490 	nvkm_wr32(device, NV10_PGRAPH_XFMODE1, xfmode1);  in nv17_gr_mthd_lma_window()
497 	nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0);  in nv17_gr_mthd_lma_window()
498 	nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);  in nv17_gr_mthd_lma_window()
591 	nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000);  in nv10_gr_load_pipe()
592 	nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000);  in nv10_gr_load_pipe()
593 	nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);  in nv10_gr_load_pipe()
595 		nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000);  in nv10_gr_load_pipe()
597 		nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);  in nv10_gr_load_pipe()
599 	nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);  in nv10_gr_load_pipe()
601 		nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000);  in nv10_gr_load_pipe()
603 	nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);  in nv10_gr_load_pipe()
605 		nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);  in nv10_gr_load_pipe()
607 	nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);  in nv10_gr_load_pipe()
608 	nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000008);  in nv10_gr_load_pipe()
615 	nvkm_wr32(device, NV10_PGRAPH_XFMODE0, xfmode0);  in nv10_gr_load_pipe()
616 	nvkm_wr32(device, NV10_PGRAPH_XFMODE1, xfmode1);  in nv10_gr_load_pipe()
854 		nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(i),  in nv10_gr_load_dma_vtxbuf()
859 	nvkm_wr32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0);  in nv10_gr_load_dma_vtxbuf()
860 	nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2,  in nv10_gr_load_dma_vtxbuf()
862 	nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DL, inst);  in nv10_gr_load_dma_vtxbuf()
869 		nvkm_wr32(device, 0x4007a0 + 4 * i, fifo[i]);  in nv10_gr_load_dma_vtxbuf()
871 	nvkm_wr32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr);  in nv10_gr_load_dma_vtxbuf()
872 	nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2, st2);  in nv10_gr_load_dma_vtxbuf()
873 	nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl);  in nv10_gr_load_dma_vtxbuf()
874 	nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh);  in nv10_gr_load_dma_vtxbuf()
878 		nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]);  in nv10_gr_load_dma_vtxbuf()
879 	nvkm_wr32(device, NV10_PGRAPH_CTX_USER, ctx_user);  in nv10_gr_load_dma_vtxbuf()
891 		nvkm_wr32(device, nv10_gr_ctx_regs[i], chan->nv10[i]);  in nv10_gr_load_context()
895 			nvkm_wr32(device, nv17_gr_ctx_regs[i], chan->nv17[i]);  in nv10_gr_load_context()
903 	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10010100);  in nv10_gr_load_context()
926 	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000000);  in nv10_gr_unload_context()
1059 	nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit);  in nv10_gr_tile()
1060 	nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch);  in nv10_gr_tile()
1061 	nvkm_wr32(device, NV10_PGRAPH_TILE(i), tile->addr);  in nv10_gr_tile()
1111 		nvkm_wr32(device, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);  in nv10_gr_intr()
1117 	nvkm_wr32(device, NV03_PGRAPH_INTR, stat);  in nv10_gr_intr()
1118 	nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);  in nv10_gr_intr()
1141 	nvkm_wr32(device, NV03_PGRAPH_INTR   , 0xFFFFFFFF);  in nv10_gr_init()
1142 	nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);  in nv10_gr_init()
1144 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);  in nv10_gr_init()
1145 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);  in nv10_gr_init()
1146 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);  in nv10_gr_init()
1148 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x25f92ad9);  in nv10_gr_init()
1149 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31));  in nv10_gr_init()
1152 		nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x1f000000);  in nv10_gr_init()
1153 		nvkm_wr32(device, 0x400a10, 0x03ff3fb6);  in nv10_gr_init()
1154 		nvkm_wr32(device, 0x400838, 0x002f8684);  in nv10_gr_init()
1155 		nvkm_wr32(device, 0x40083c, 0x00115f3f);  in nv10_gr_init()
1156 		nvkm_wr32(device, 0x4006b0, 0x40000020);  in nv10_gr_init()
1158 		nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);  in nv10_gr_init()
1161 	nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000);  in nv10_gr_init()
1162 	nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000);  in nv10_gr_init()
1163 	nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000);  in nv10_gr_init()
1164 	nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000);  in nv10_gr_init()
1165 	nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000);  in nv10_gr_init()
1166 	nvkm_wr32(device, NV10_PGRAPH_STATE, 0xFFFFFFFF);  in nv10_gr_init()
1169 	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);  in nv10_gr_init()
1170 	nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2, 0x08000000);  in nv10_gr_init()