Lines Matching refs:cp_ctx
164 cp_ctx(ctx, 0x4000a4, 1); in nv40_gr_construct_general()
166 cp_ctx(ctx, 0x400144, 58); in nv40_gr_construct_general()
168 cp_ctx(ctx, 0x400314, 1); in nv40_gr_construct_general()
170 cp_ctx(ctx, 0x400400, 10); in nv40_gr_construct_general()
171 cp_ctx(ctx, 0x400480, 10); in nv40_gr_construct_general()
172 cp_ctx(ctx, 0x400500, 19); in nv40_gr_construct_general()
178 cp_ctx(ctx, 0x400560, 6); in nv40_gr_construct_general()
181 cp_ctx(ctx, 0x40057c, 5); in nv40_gr_construct_general()
182 cp_ctx(ctx, 0x400710, 3); in nv40_gr_construct_general()
185 cp_ctx(ctx, 0x400724, 1); in nv40_gr_construct_general()
187 cp_ctx(ctx, 0x400770, 3); in nv40_gr_construct_general()
189 cp_ctx(ctx, 0x400814, 4); in nv40_gr_construct_general()
190 cp_ctx(ctx, 0x400828, 5); in nv40_gr_construct_general()
191 cp_ctx(ctx, 0x400840, 5); in nv40_gr_construct_general()
193 cp_ctx(ctx, 0x400858, 4); in nv40_gr_construct_general()
197 cp_ctx(ctx, 0x40086c, 9); in nv40_gr_construct_general()
204 cp_ctx(ctx, 0x4009c0, 8); in nv40_gr_construct_general()
208 cp_ctx(ctx, 0x400840, 20); in nv40_gr_construct_general()
216 cp_ctx(ctx, 0x400894, 11); in nv40_gr_construct_general()
222 cp_ctx(ctx, 0x4008e0, 2); in nv40_gr_construct_general()
223 cp_ctx(ctx, 0x4008f8, 2); in nv40_gr_construct_general()
226 cp_ctx(ctx, 0x4009f8, 1); in nv40_gr_construct_general()
228 cp_ctx(ctx, 0x400a00, 73); in nv40_gr_construct_general()
230 cp_ctx(ctx, 0x401000, 4); in nv40_gr_construct_general()
231 cp_ctx(ctx, 0x405004, 1); in nv40_gr_construct_general()
236 cp_ctx(ctx, 0x403448, 1); in nv40_gr_construct_general()
240 cp_ctx(ctx, 0x403440, 1); in nv40_gr_construct_general()
271 cp_ctx(ctx, 0x401880, 51); in nv40_gr_construct_state3d()
276 cp_ctx(ctx, 0x401880, 32); in nv40_gr_construct_state3d()
280 cp_ctx(ctx, 0x401900, 16); in nv40_gr_construct_state3d()
281 cp_ctx(ctx, 0x401940, 3); in nv40_gr_construct_state3d()
283 cp_ctx(ctx, 0x40194c, 18); in nv40_gr_construct_state3d()
291 cp_ctx(ctx, 0x4019a0, 2); in nv40_gr_construct_state3d()
292 cp_ctx(ctx, 0x4019ac, 5); in nv40_gr_construct_state3d()
294 cp_ctx(ctx, 0x4019a0, 1); in nv40_gr_construct_state3d()
295 cp_ctx(ctx, 0x4019b4, 3); in nv40_gr_construct_state3d()
303 cp_ctx(ctx, 0x4019c0, 18); in nv40_gr_construct_state3d()
308 cp_ctx(ctx, 0x401a08, 8); in nv40_gr_construct_state3d()
312 cp_ctx(ctx, 0x401a2c, 4); in nv40_gr_construct_state3d()
313 cp_ctx(ctx, 0x401a44, 26); in nv40_gr_construct_state3d()
318 cp_ctx(ctx, 0x401ab8, 3); in nv40_gr_construct_state3d()
320 cp_ctx(ctx, 0x401ab8, 1); in nv40_gr_construct_state3d()
321 cp_ctx(ctx, 0x401ac0, 1); in nv40_gr_construct_state3d()
323 cp_ctx(ctx, 0x401ad0, 8); in nv40_gr_construct_state3d()
328 cp_ctx(ctx, 0x401b10, device->chipset == 0x40 ? 2 : 1); in nv40_gr_construct_state3d()
330 cp_ctx(ctx, 0x401b18, device->chipset == 0x40 ? 6 : 5); in nv40_gr_construct_state3d()
333 cp_ctx(ctx, 0x401b30, 25); in nv40_gr_construct_state3d()
344 cp_ctx(ctx, 0x401b94, 1); in nv40_gr_construct_state3d()
345 cp_ctx(ctx, 0x401b98, 8); in nv40_gr_construct_state3d()
347 cp_ctx(ctx, 0x401bc0, 9); in nv40_gr_construct_state3d()
349 cp_ctx(ctx, 0x401c00, 192); in nv40_gr_construct_state3d()
364 cp_ctx(ctx, 0x400f5c, 3); in nv40_gr_construct_state3d()
366 cp_ctx(ctx, 0x400f84, 1); in nv40_gr_construct_state3d()
375 cp_ctx(ctx, 0x402000, 1); in nv40_gr_construct_state3d_2()
376 cp_ctx(ctx, 0x402404, device->chipset == 0x40 ? 1 : 2); in nv40_gr_construct_state3d_2()
403 cp_ctx(ctx, 0x402440, 1); in nv40_gr_construct_state3d_2()
409 cp_ctx(ctx, 0x402480, device->chipset == 0x40 ? 8 : 9); in nv40_gr_construct_state3d_2()
431 cp_ctx(ctx, 0x402500, 31); in nv40_gr_construct_state3d_2()
434 cp_ctx(ctx, 0x40257c, 6); in nv40_gr_construct_state3d_2()
435 cp_ctx(ctx, 0x402594, 16); in nv40_gr_construct_state3d_2()
436 cp_ctx(ctx, 0x402800, 17); in nv40_gr_construct_state3d_2()
442 cp_ctx(ctx, 0x402864, 1); in nv40_gr_construct_state3d_2()
444 cp_ctx(ctx, 0x402870, 3); in nv40_gr_construct_state3d_2()
447 cp_ctx(ctx, 0x402900, 1); in nv40_gr_construct_state3d_2()
448 cp_ctx(ctx, 0x402940, 1); in nv40_gr_construct_state3d_2()
449 cp_ctx(ctx, 0x402980, 1); in nv40_gr_construct_state3d_2()
450 cp_ctx(ctx, 0x4029c0, 1); in nv40_gr_construct_state3d_2()
451 cp_ctx(ctx, 0x402a00, 1); in nv40_gr_construct_state3d_2()
452 cp_ctx(ctx, 0x402a40, 1); in nv40_gr_construct_state3d_2()
453 cp_ctx(ctx, 0x402a80, 1); in nv40_gr_construct_state3d_2()
454 cp_ctx(ctx, 0x402ac0, 1); in nv40_gr_construct_state3d_2()
458 cp_ctx(ctx, 0x402844, 1); in nv40_gr_construct_state3d_2()
460 cp_ctx(ctx, 0x402850, 1); in nv40_gr_construct_state3d_2()
463 cp_ctx(ctx, 0x402844, 1); in nv40_gr_construct_state3d_2()
465 cp_ctx(ctx, 0x402850, 2); in nv40_gr_construct_state3d_2()
470 cp_ctx(ctx, 0x402c00, 4); in nv40_gr_construct_state3d_2()
477 cp_ctx(ctx, 0x402c20, 40); in nv40_gr_construct_state3d_2()
480 cp_ctx(ctx, 0x4030b8, 13); in nv40_gr_construct_state3d_2()
485 cp_ctx(ctx, 0x402c10, 4); in nv40_gr_construct_state3d_2()
487 cp_ctx(ctx, 0x402c20, 36); in nv40_gr_construct_state3d_2()
490 cp_ctx(ctx, 0x402c20, 24); in nv40_gr_construct_state3d_2()
493 cp_ctx(ctx, 0x402c20, 16); in nv40_gr_construct_state3d_2()
495 cp_ctx(ctx, 0x402c20, 8); in nv40_gr_construct_state3d_2()
496 cp_ctx(ctx, 0x402cb0, device->chipset == 0x40 ? 12 : 13); in nv40_gr_construct_state3d_2()
503 cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3); in nv40_gr_construct_state3d_2()
504 cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3); in nv40_gr_construct_state3d_2()
505 cp_ctx(ctx, 0x403420, nv40_gr_vs_count(ctx->device)); in nv40_gr_construct_state3d_2()
510 cp_ctx(ctx, 0x403600, 1); in nv40_gr_construct_state3d_2()
513 cp_ctx(ctx, 0x403800, 1); in nv40_gr_construct_state3d_2()
515 cp_ctx(ctx, 0x403c18, 1); in nv40_gr_construct_state3d_2()
522 cp_ctx(ctx, 0x405018, 1); in nv40_gr_construct_state3d_2()
524 cp_ctx(ctx, 0x405c24, 1); in nv40_gr_construct_state3d_2()
529 cp_ctx(ctx, 0x405800, 11); in nv40_gr_construct_state3d_2()
530 cp_ctx(ctx, 0x407000, 1); in nv40_gr_construct_state3d_2()