Lines Matching refs:nvkm_wr32
58 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000000); in nv04_fifo_pause()
78 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); in nv04_fifo_pause()
80 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0x00000000); in nv04_fifo_pause()
92 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000001); in nv04_fifo_start()
151 nvkm_wr32(device, 0x003280, (engine &= ~mask)); in nv04_fifo_swmthd()
204 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0); in nv04_fifo_cache_error()
205 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); in nv04_fifo_cache_error()
207 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, in nv04_fifo_cache_error()
209 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); in nv04_fifo_cache_error()
210 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, in nv04_fifo_cache_error()
212 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0); in nv04_fifo_cache_error()
214 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, in nv04_fifo_cache_error()
216 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_cache_error()
248 nvkm_wr32(device, 0x003364, 0x00000000); in nv04_fifo_dma_pusher()
250 nvkm_wr32(device, 0x003244, dma_put); in nv04_fifo_dma_pusher()
251 nvkm_wr32(device, 0x003328, ho_put); in nv04_fifo_dma_pusher()
254 nvkm_wr32(device, 0x003334, ib_put); in nv04_fifo_dma_pusher()
262 nvkm_wr32(device, 0x003244, dma_put); in nv04_fifo_dma_pusher()
266 nvkm_wr32(device, 0x003228, 0x00000000); in nv04_fifo_dma_pusher()
267 nvkm_wr32(device, 0x003220, 0x00000001); in nv04_fifo_dma_pusher()
268 nvkm_wr32(device, 0x002100, NV_PFIFO_INTR_DMA_PUSHER); in nv04_fifo_dma_pusher()
282 nvkm_wr32(device, NV03_PFIFO_CACHES, 0); in nv04_fifo_intr()
299 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE); in nv04_fifo_intr()
302 nvkm_wr32(device, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); in nv04_fifo_intr()
304 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); in nv04_fifo_intr()
305 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_intr()
311 nvkm_wr32(device, 0x002100, 0x00000010); in nv04_fifo_intr()
315 nvkm_wr32(device, 0x002100, 0x40000000); in nv04_fifo_intr()
324 nvkm_wr32(device, NV03_PFIFO_INTR_0, stat); in nv04_fifo_intr()
327 nvkm_wr32(device, NV03_PFIFO_CACHES, reassign); in nv04_fifo_intr()
340 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); in nv04_fifo_init()
341 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); in nv04_fifo_init()
343 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | in nv04_fifo_init()
346 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); in nv04_fifo_init()
347 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8); in nv04_fifo_init()
349 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); in nv04_fifo_init()
351 nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); in nv04_fifo_init()
352 nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); in nv04_fifo_init()
354 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); in nv04_fifo_init()
355 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_init()
356 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); in nv04_fifo_init()