177 	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];  member
228 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)  in _dpu_encoder_setup_dither()  argument
232 	if (!hw_pp->ops.setup_dither)  in _dpu_encoder_setup_dither()
244 		hw_pp->ops.setup_dither(hw_pp, NULL);  in _dpu_encoder_setup_dither()
251 	hw_pp->ops.setup_dither(hw_pp, &dither_cfg);  in _dpu_encoder_setup_dither()
277 			phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);  in dpu_encoder_helper_report_irq_timeout()
318 		      irq, phys_enc->hw_pp->idx - PINGPONG_0,  in dpu_encoder_helper_wait_for_irq()
334 				      phys_enc->hw_pp->idx - PINGPONG_0,  in dpu_encoder_helper_wait_for_irq()
345 				      phys_enc->hw_pp->idx - PINGPONG_0,  in dpu_encoder_helper_wait_for_irq()
352 			phys_enc->hw_pp->idx - PINGPONG_0,  in dpu_encoder_helper_wait_for_irq()
618 	} else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {  in _dpu_encoder_update_vsync_source()
621 				(int) ARRAY_SIZE(dpu_enc->hw_pp));  in _dpu_encoder_update_vsync_source()
639 			vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;  in _dpu_encoder_update_vsync_source()
963 	struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];  in dpu_encoder_virt_atomic_mode_set()  local
993 		drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,  in dpu_encoder_virt_atomic_mode_set()
994 		ARRAY_SIZE(hw_pp));  in dpu_encoder_virt_atomic_mode_set()
1004 		dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])  in dpu_encoder_virt_atomic_mode_set()
1036 		if (!dpu_enc->hw_pp[i]) {  in dpu_encoder_virt_atomic_mode_set()
1048 		phys->hw_pp = dpu_enc->hw_pp[i];  in dpu_encoder_virt_atomic_mode_set()
1086 			if (!dpu_enc->hw_pp[i])  in _dpu_encoder_virt_enable_helper()
1088 			_dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);  in _dpu_encoder_virt_enable_helper()
1397 	if (!phys->hw_pp) {  in _dpu_encoder_trigger_flush()
1436 	if (!phys->hw_pp) {  in _dpu_encoder_trigger_start()
1756 				     struct dpu_hw_pingpong *hw_pp,  in dpu_encoder_dsc_pipe_cfg()  argument
1767 	if (hw_pp->ops.setup_dsc)  in dpu_encoder_dsc_pipe_cfg()
1768 		hw_pp->ops.setup_dsc(hw_pp);  in dpu_encoder_dsc_pipe_cfg()
1770 	if (hw_pp->ops.enable_dsc)  in dpu_encoder_dsc_pipe_cfg()
1771 		hw_pp->ops.enable_dsc(hw_pp);  in dpu_encoder_dsc_pipe_cfg()
1780 	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];  in dpu_encoder_prep_dsc()  local
1789 		hw_pp[i] = dpu_enc->hw_pp[i];  in dpu_encoder_prep_dsc()
1792 		if (!hw_pp[i] || !hw_dsc[i]) {  in dpu_encoder_prep_dsc()
1815 		dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode, initial_lines);  in dpu_encoder_prep_dsc()
1971 					phys_enc->hw_pp->idx);  in dpu_encoder_helper_phys_cleanup()
1981 						dpu_enc->phys_encs[i]->hw_pp->idx);  in dpu_encoder_helper_phys_cleanup()
1991 	if (phys_enc->hw_pp->merge_3d) {  in dpu_encoder_helper_phys_cleanup()
1992 		phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,  in dpu_encoder_helper_phys_cleanup()
1996 					phys_enc->hw_pp->merge_3d->idx);  in dpu_encoder_helper_phys_cleanup()
2007 	if (phys_enc->hw_pp->merge_3d)  in dpu_encoder_helper_phys_cleanup()
2008 		intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;  in dpu_encoder_helper_phys_cleanup()