488 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)  in CP_LOAD_STATE_0_DST_OFF()  argument
490 	return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;  in CP_LOAD_STATE_0_DST_OFF()
494 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)  in CP_LOAD_STATE_0_STATE_SRC()  argument
496 	return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;  in CP_LOAD_STATE_0_STATE_SRC()
500 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)  in CP_LOAD_STATE_0_STATE_BLOCK()  argument
502 	return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;  in CP_LOAD_STATE_0_STATE_BLOCK()
506 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)  in CP_LOAD_STATE_0_NUM_UNIT()  argument
508 	return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;  in CP_LOAD_STATE_0_NUM_UNIT()
514 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)  in CP_LOAD_STATE_1_STATE_TYPE()  argument
516 	return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;  in CP_LOAD_STATE_1_STATE_TYPE()
520 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)  in CP_LOAD_STATE_1_EXT_SRC_ADDR()  argument
522 	return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;  in CP_LOAD_STATE_1_EXT_SRC_ADDR()
528 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)  in CP_LOAD_STATE4_0_DST_OFF()  argument
530 	return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;  in CP_LOAD_STATE4_0_DST_OFF()
534 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)  in CP_LOAD_STATE4_0_STATE_SRC()  argument
536 	return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;  in CP_LOAD_STATE4_0_STATE_SRC()
540 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)  in CP_LOAD_STATE4_0_STATE_BLOCK()  argument
542 	return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;  in CP_LOAD_STATE4_0_STATE_BLOCK()
546 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)  in CP_LOAD_STATE4_0_NUM_UNIT()  argument
548 	return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;  in CP_LOAD_STATE4_0_NUM_UNIT()
554 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)  in CP_LOAD_STATE4_1_STATE_TYPE()  argument
556 	return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;  in CP_LOAD_STATE4_1_STATE_TYPE()
560 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)  in CP_LOAD_STATE4_1_EXT_SRC_ADDR()  argument
562 	return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;  in CP_LOAD_STATE4_1_EXT_SRC_ADDR()
568 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)  in CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI()  argument
570 	return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;  in CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI()
576 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)  in CP_LOAD_STATE6_0_DST_OFF()  argument
578 	return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;  in CP_LOAD_STATE6_0_DST_OFF()
582 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)  in CP_LOAD_STATE6_0_STATE_TYPE()  argument
584 	return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;  in CP_LOAD_STATE6_0_STATE_TYPE()
588 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)  in CP_LOAD_STATE6_0_STATE_SRC()  argument
590 	return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;  in CP_LOAD_STATE6_0_STATE_SRC()
594 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)  in CP_LOAD_STATE6_0_STATE_BLOCK()  argument
596 	return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;  in CP_LOAD_STATE6_0_STATE_BLOCK()
600 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)  in CP_LOAD_STATE6_0_NUM_UNIT()  argument
602 	return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;  in CP_LOAD_STATE6_0_NUM_UNIT()
608 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)  in CP_LOAD_STATE6_1_EXT_SRC_ADDR()  argument
610 	return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;  in CP_LOAD_STATE6_1_EXT_SRC_ADDR()
616 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)  in CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI()  argument
618 	return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;  in CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI()
626 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)  in CP_DRAW_INDX_0_VIZ_QUERY()  argument
628 	return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;  in CP_DRAW_INDX_0_VIZ_QUERY()
634 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_1_PRIM_TYPE()  argument
636 	return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;  in CP_DRAW_INDX_1_PRIM_TYPE()
640 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_1_SOURCE_SELECT()  argument
642 	return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;  in CP_DRAW_INDX_1_SOURCE_SELECT()
646 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_1_VIS_CULL()  argument
648 	return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;  in CP_DRAW_INDX_1_VIS_CULL()
652 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)  in CP_DRAW_INDX_1_INDEX_SIZE()  argument
654 	return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;  in CP_DRAW_INDX_1_INDEX_SIZE()
661 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)  in CP_DRAW_INDX_1_NUM_INSTANCES()  argument
663 	return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;  in CP_DRAW_INDX_1_NUM_INSTANCES()
669 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)  in CP_DRAW_INDX_2_NUM_INDICES()  argument
671 	return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;  in CP_DRAW_INDX_2_NUM_INDICES()
677 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)  in CP_DRAW_INDX_3_INDX_BASE()  argument
679 	return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;  in CP_DRAW_INDX_3_INDX_BASE()
685 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)  in CP_DRAW_INDX_4_INDX_SIZE()  argument
687 	return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;  in CP_DRAW_INDX_4_INDX_SIZE()
693 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)  in CP_DRAW_INDX_2_0_VIZ_QUERY()  argument
695 	return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;  in CP_DRAW_INDX_2_0_VIZ_QUERY()
701 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_2_1_PRIM_TYPE()  argument
703 	return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;  in CP_DRAW_INDX_2_1_PRIM_TYPE()
707 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_2_1_SOURCE_SELECT()  argument
709 	return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;  in CP_DRAW_INDX_2_1_SOURCE_SELECT()
713 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_2_1_VIS_CULL()  argument
715 	return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;  in CP_DRAW_INDX_2_1_VIS_CULL()
719 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)  in CP_DRAW_INDX_2_1_INDEX_SIZE()  argument
721 	return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;  in CP_DRAW_INDX_2_1_INDEX_SIZE()
728 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)  in CP_DRAW_INDX_2_1_NUM_INSTANCES()  argument
730 	return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;  in CP_DRAW_INDX_2_1_NUM_INSTANCES()
736 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)  in CP_DRAW_INDX_2_2_NUM_INDICES()  argument
738 	return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;  in CP_DRAW_INDX_2_2_NUM_INDICES()
744 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_OFFSET_0_PRIM_TYPE()  argument
746 	return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;  in CP_DRAW_INDX_OFFSET_0_PRIM_TYPE()
750 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT()  argument
752 …return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT…  in CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT()
756 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_OFFSET_0_VIS_CULL()  argument
758 	return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;  in CP_DRAW_INDX_OFFSET_0_VIS_CULL()
762 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)  in CP_DRAW_INDX_OFFSET_0_INDEX_SIZE()  argument
764 	return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;  in CP_DRAW_INDX_OFFSET_0_INDEX_SIZE()
768 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)  in CP_DRAW_INDX_OFFSET_0_PATCH_TYPE()  argument
770 	return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK;  in CP_DRAW_INDX_OFFSET_0_PATCH_TYPE()
778 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)  in CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES()  argument
780 …return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES…  in CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES()
786 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)  in CP_DRAW_INDX_OFFSET_2_NUM_INDICES()  argument
788 …return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MA…  in CP_DRAW_INDX_OFFSET_2_NUM_INDICES()
794 static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)  in CP_DRAW_INDX_OFFSET_3_FIRST_INDX()  argument
796 	return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK;  in CP_DRAW_INDX_OFFSET_3_FIRST_INDX()
803 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)  in CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO()  argument
805 …return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__…  in CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO()
811 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)  in CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI()  argument
813 …return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__…  in CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI()
821 static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)  in CP_DRAW_INDX_OFFSET_6_MAX_INDICES()  argument
823 …return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MA…  in CP_DRAW_INDX_OFFSET_6_MAX_INDICES()
829 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)  in CP_DRAW_INDX_OFFSET_4_INDX_BASE()  argument
831 	return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;  in CP_DRAW_INDX_OFFSET_4_INDX_BASE()
837 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)  in CP_DRAW_INDX_OFFSET_5_INDX_SIZE()  argument
839 	return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;  in CP_DRAW_INDX_OFFSET_5_INDX_SIZE()
845 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)  in A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE()  argument
847 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MA…  in A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE()
851 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT()  argument
853 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SE…  in A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT()
857 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A4XX_CP_DRAW_INDIRECT_0_VIS_CULL()  argument
859 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;  in A4XX_CP_DRAW_INDIRECT_0_VIS_CULL()
863 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)  in A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE()  argument
865 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__…  in A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE()
869 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)  in A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE()  argument
871 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__…  in A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE()
880 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)  in A4XX_CP_DRAW_INDIRECT_1_INDIRECT()  argument
882 	return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;  in A4XX_CP_DRAW_INDIRECT_1_INDIRECT()
889 static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)  in A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO()  argument
891 …return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO…  in A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO()
897 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)  in A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI()  argument
899 …return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI…  in A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI()
907 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE()  argument
909 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRI…  in A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE()
913 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT()  argument
915 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0…  in A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT()
919 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL()  argument
921 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_…  in A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL()
925 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE()  argument
927 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_IN…  in A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE()
931 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE()  argument
933 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PA…  in A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE()
942 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)  in A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE()  argument
944 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_IND…  in A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE()
950 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)  in A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE()  argument
952 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_IND…  in A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE()
958 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)  in A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT()  argument
960 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDI…  in A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT()
967 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO()  argument
969 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_…  in A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO()
975 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI()  argument
977 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_…  in A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI()
985 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES()  argument
987 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_M…  in A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES()
993 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO()  argument
995 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_I…  in A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO()
1001 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI()  argument
1003 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_I…  in A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI()
1011 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE()  argument
1013 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_P…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE()
1017 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT()  argument
1019 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT()
1023 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL()  argument
1025 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VI…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL()
1029 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE()  argument
1031 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE()
1035 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE()  argument
1037 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE()
1045 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)  in A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE()  argument
1047 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCO…  in A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE()
1051 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)  in A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF()  argument
1053 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST…  in A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF()
1099 static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val)  in CP_DRAW_PRED_SET_0_SRC()  argument
1101 	return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK;  in CP_DRAW_PRED_SET_0_SRC()
1105 static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val)  in CP_DRAW_PRED_SET_0_TEST()  argument
1107 	return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK;  in CP_DRAW_PRED_SET_0_TEST()
1117 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)  in CP_SET_DRAW_STATE__0_COUNT()  argument
1119 	return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;  in CP_SET_DRAW_STATE__0_COUNT()
1130 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)  in CP_SET_DRAW_STATE__0_GROUP_ID()  argument
1132 	return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;  in CP_SET_DRAW_STATE__0_GROUP_ID()
1138 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)  in CP_SET_DRAW_STATE__1_ADDR_LO()  argument
1140 	return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;  in CP_SET_DRAW_STATE__1_ADDR_LO()
1146 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)  in CP_SET_DRAW_STATE__2_ADDR_HI()  argument
1148 	return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;  in CP_SET_DRAW_STATE__2_ADDR_HI()
1156 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)  in CP_SET_BIN_1_X1()  argument
1158 	return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;  in CP_SET_BIN_1_X1()
1162 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)  in CP_SET_BIN_1_Y1()  argument
1164 	return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;  in CP_SET_BIN_1_Y1()
1170 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)  in CP_SET_BIN_2_X2()  argument
1172 	return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;  in CP_SET_BIN_2_X2()
1176 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)  in CP_SET_BIN_2_Y2()  argument
1178 	return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;  in CP_SET_BIN_2_Y2()
1184 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)  in CP_SET_BIN_DATA_0_BIN_DATA_ADDR()  argument
1186 	return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;  in CP_SET_BIN_DATA_0_BIN_DATA_ADDR()
1192 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)  in CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS()  argument
1194 …return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__…  in CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS()
1200 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)  in CP_SET_BIN_DATA5_0_VSC_SIZE()  argument
1202 	return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;  in CP_SET_BIN_DATA5_0_VSC_SIZE()
1206 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)  in CP_SET_BIN_DATA5_0_VSC_N()  argument
1208 	return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;  in CP_SET_BIN_DATA5_0_VSC_N()
1214 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)  in CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO()  argument
1216 …return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO…  in CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO()
1222 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)  in CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI()  argument
1224 …return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI…  in CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI()
1230 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)  in CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO()  argument
1232 …return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDR…  in CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO()
1238 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)  in CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI()  argument
1240 …return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDR…  in CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI()
1246 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)  in CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO()  argument
1248 …return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO…  in CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO()
1254 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)  in CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI()  argument
1256 …return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI…  in CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI()
1262 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE()  argument
1264 …return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__…  in CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE()
1268 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_0_VSC_N()  argument
1270 	return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK;  in CP_SET_BIN_DATA5_OFFSET_0_VSC_N()
1276 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET()  argument
1278 …return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN…  in CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET()
1284 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET()  argument
1286 …return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN…  in CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET()
1292 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET()  argument
1294 …return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BI…  in CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET()
1300 static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val)  in CP_REG_RMW_0_DST_REG()  argument
1302 	return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK;  in CP_REG_RMW_0_DST_REG()
1306 static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val)  in CP_REG_RMW_0_ROTATE()  argument
1308 	return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK;  in CP_REG_RMW_0_ROTATE()
1317 static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val)  in CP_REG_RMW_1_SRC0()  argument
1319 	return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK;  in CP_REG_RMW_1_SRC0()
1325 static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val)  in CP_REG_RMW_2_SRC1()  argument
1327 	return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK;  in CP_REG_RMW_2_SRC1()
1333 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)  in CP_REG_TO_MEM_0_REG()  argument
1335 	return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;  in CP_REG_TO_MEM_0_REG()
1339 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)  in CP_REG_TO_MEM_0_CNT()  argument
1341 	return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;  in CP_REG_TO_MEM_0_CNT()
1349 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)  in CP_REG_TO_MEM_1_DEST()  argument
1351 	return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;  in CP_REG_TO_MEM_1_DEST()
1357 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)  in CP_REG_TO_MEM_2_DEST_HI()  argument
1359 	return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;  in CP_REG_TO_MEM_2_DEST_HI()
1365 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_0_REG()  argument
1367 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK;  in CP_REG_TO_MEM_OFFSET_REG_0_REG()
1371 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_0_CNT()  argument
1373 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK;  in CP_REG_TO_MEM_OFFSET_REG_0_CNT()
1381 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_1_DEST()  argument
1383 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK;  in CP_REG_TO_MEM_OFFSET_REG_1_DEST()
1389 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI()  argument
1391 …return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__…  in CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI()
1397 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0()  argument
1399 …return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__…  in CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0()
1406 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_0_REG()  argument
1408 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK;  in CP_REG_TO_MEM_OFFSET_MEM_0_REG()
1412 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_0_CNT()  argument
1414 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK;  in CP_REG_TO_MEM_OFFSET_MEM_0_CNT()
1422 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_1_DEST()  argument
1424 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK;  in CP_REG_TO_MEM_OFFSET_MEM_1_DEST()
1430 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI()  argument
1432 …return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__…  in CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI()
1438 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO()  argument
1440 …return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_…  in CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO()
1446 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI()  argument
1448 …return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_…  in CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI()
1454 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)  in CP_MEM_TO_REG_0_REG()  argument
1456 	return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;  in CP_MEM_TO_REG_0_REG()
1460 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)  in CP_MEM_TO_REG_0_CNT()  argument
1462 	return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;  in CP_MEM_TO_REG_0_CNT()
1470 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)  in CP_MEM_TO_REG_1_SRC()  argument
1472 	return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;  in CP_MEM_TO_REG_1_SRC()
1478 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)  in CP_MEM_TO_REG_2_SRC_HI()  argument
1480 	return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;  in CP_MEM_TO_REG_2_SRC_HI()
1494 static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val)  in CP_MEMCPY_0_DWORDS()  argument
1496 	return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK;  in CP_MEMCPY_0_DWORDS()
1502 static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val)  in CP_MEMCPY_1_SRC_LO()  argument
1504 	return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK;  in CP_MEMCPY_1_SRC_LO()
1510 static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val)  in CP_MEMCPY_2_SRC_HI()  argument
1512 	return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK;  in CP_MEMCPY_2_SRC_HI()
1518 static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val)  in CP_MEMCPY_3_DST_LO()  argument
1520 	return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK;  in CP_MEMCPY_3_DST_LO()
1526 static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val)  in CP_MEMCPY_4_DST_HI()  argument
1528 	return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK;  in CP_MEMCPY_4_DST_HI()
1534 static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val)  in CP_REG_TO_SCRATCH_0_REG()  argument
1536 	return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK;  in CP_REG_TO_SCRATCH_0_REG()
1540 static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)  in CP_REG_TO_SCRATCH_0_SCRATCH()  argument
1542 	return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK;  in CP_REG_TO_SCRATCH_0_SCRATCH()
1546 static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val)  in CP_REG_TO_SCRATCH_0_CNT()  argument
1548 	return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK;  in CP_REG_TO_SCRATCH_0_CNT()
1554 static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val)  in CP_SCRATCH_TO_REG_0_REG()  argument
1556 	return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK;  in CP_SCRATCH_TO_REG_0_REG()
1561 static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)  in CP_SCRATCH_TO_REG_0_SCRATCH()  argument
1563 	return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK;  in CP_SCRATCH_TO_REG_0_SCRATCH()
1567 static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val)  in CP_SCRATCH_TO_REG_0_CNT()  argument
1569 	return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK;  in CP_SCRATCH_TO_REG_0_CNT()
1575 static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)  in CP_SCRATCH_WRITE_0_SCRATCH()  argument
1577 	return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK;  in CP_SCRATCH_WRITE_0_SCRATCH()
1583 static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val)  in CP_MEM_WRITE_0_ADDR_LO()  argument
1585 	return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK;  in CP_MEM_WRITE_0_ADDR_LO()
1591 static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val)  in CP_MEM_WRITE_1_ADDR_HI()  argument
1593 	return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK;  in CP_MEM_WRITE_1_ADDR_HI()
1599 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)  in CP_COND_WRITE_0_FUNCTION()  argument
1601 	return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;  in CP_COND_WRITE_0_FUNCTION()
1609 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)  in CP_COND_WRITE_1_POLL_ADDR()  argument
1611 	return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;  in CP_COND_WRITE_1_POLL_ADDR()
1617 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)  in CP_COND_WRITE_2_REF()  argument
1619 	return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;  in CP_COND_WRITE_2_REF()
1625 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)  in CP_COND_WRITE_3_MASK()  argument
1627 	return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;  in CP_COND_WRITE_3_MASK()
1633 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)  in CP_COND_WRITE_4_WRITE_ADDR()  argument
1635 	return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;  in CP_COND_WRITE_4_WRITE_ADDR()
1641 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)  in CP_COND_WRITE_5_WRITE_DATA()  argument
1643 	return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;  in CP_COND_WRITE_5_WRITE_DATA()
1649 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)  in CP_COND_WRITE5_0_FUNCTION()  argument
1651 	return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;  in CP_COND_WRITE5_0_FUNCTION()
1661 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)  in CP_COND_WRITE5_1_POLL_ADDR_LO()  argument
1663 	return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;  in CP_COND_WRITE5_1_POLL_ADDR_LO()
1669 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)  in CP_COND_WRITE5_2_POLL_ADDR_HI()  argument
1671 	return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;  in CP_COND_WRITE5_2_POLL_ADDR_HI()
1677 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)  in CP_COND_WRITE5_3_REF()  argument
1679 	return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;  in CP_COND_WRITE5_3_REF()
1685 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)  in CP_COND_WRITE5_4_MASK()  argument
1687 	return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;  in CP_COND_WRITE5_4_MASK()
1693 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)  in CP_COND_WRITE5_5_WRITE_ADDR_LO()  argument
1695 	return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;  in CP_COND_WRITE5_5_WRITE_ADDR_LO()
1701 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)  in CP_COND_WRITE5_6_WRITE_ADDR_HI()  argument
1703 	return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;  in CP_COND_WRITE5_6_WRITE_ADDR_HI()
1709 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)  in CP_COND_WRITE5_7_WRITE_DATA()  argument
1711 	return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;  in CP_COND_WRITE5_7_WRITE_DATA()
1717 static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)  in CP_WAIT_MEM_GTE_0_RESERVED()  argument
1719 	return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK;  in CP_WAIT_MEM_GTE_0_RESERVED()
1725 static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)  in CP_WAIT_MEM_GTE_1_POLL_ADDR_LO()  argument
1727 	return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK;  in CP_WAIT_MEM_GTE_1_POLL_ADDR_LO()
1733 static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)  in CP_WAIT_MEM_GTE_2_POLL_ADDR_HI()  argument
1735 	return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK;  in CP_WAIT_MEM_GTE_2_POLL_ADDR_HI()
1741 static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val)  in CP_WAIT_MEM_GTE_3_REF()  argument
1743 	return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK;  in CP_WAIT_MEM_GTE_3_REF()
1749 static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)  in CP_WAIT_REG_MEM_0_FUNCTION()  argument
1751 	return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK;  in CP_WAIT_REG_MEM_0_FUNCTION()
1761 static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)  in CP_WAIT_REG_MEM_1_POLL_ADDR_LO()  argument
1763 	return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK;  in CP_WAIT_REG_MEM_1_POLL_ADDR_LO()
1769 static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)  in CP_WAIT_REG_MEM_2_POLL_ADDR_HI()  argument
1771 	return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK;  in CP_WAIT_REG_MEM_2_POLL_ADDR_HI()
1777 static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val)  in CP_WAIT_REG_MEM_3_REF()  argument
1779 	return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK;  in CP_WAIT_REG_MEM_3_REF()
1785 static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val)  in CP_WAIT_REG_MEM_4_MASK()  argument
1787 	return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK;  in CP_WAIT_REG_MEM_4_MASK()
1793 static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)  in CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES()  argument
1795 …return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES…  in CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES()
1801 static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val)  in CP_WAIT_TWO_REGS_0_REG0()  argument
1803 	return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK;  in CP_WAIT_TWO_REGS_0_REG0()
1809 static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val)  in CP_WAIT_TWO_REGS_1_REG1()  argument
1811 	return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK;  in CP_WAIT_TWO_REGS_1_REG1()
1817 static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val)  in CP_WAIT_TWO_REGS_2_REF()  argument
1819 	return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK;  in CP_WAIT_TWO_REGS_2_REF()
1827 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)  in CP_DISPATCH_COMPUTE_1_X()  argument
1829 	return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;  in CP_DISPATCH_COMPUTE_1_X()
1835 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)  in CP_DISPATCH_COMPUTE_2_Y()  argument
1837 	return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;  in CP_DISPATCH_COMPUTE_2_Y()
1843 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)  in CP_DISPATCH_COMPUTE_3_Z()  argument
1845 	return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;  in CP_DISPATCH_COMPUTE_3_Z()
1851 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)  in CP_SET_RENDER_MODE_0_MODE()  argument
1853 	return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;  in CP_SET_RENDER_MODE_0_MODE()
1859 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)  in CP_SET_RENDER_MODE_1_ADDR_0_LO()  argument
1861 	return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;  in CP_SET_RENDER_MODE_1_ADDR_0_LO()
1867 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)  in CP_SET_RENDER_MODE_2_ADDR_0_HI()  argument
1869 	return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;  in CP_SET_RENDER_MODE_2_ADDR_0_HI()
1881 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)  in CP_SET_RENDER_MODE_5_ADDR_1_LEN()  argument
1883 	return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;  in CP_SET_RENDER_MODE_5_ADDR_1_LEN()
1889 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)  in CP_SET_RENDER_MODE_6_ADDR_1_LO()  argument
1891 	return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;  in CP_SET_RENDER_MODE_6_ADDR_1_LO()
1897 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)  in CP_SET_RENDER_MODE_7_ADDR_1_HI()  argument
1899 	return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;  in CP_SET_RENDER_MODE_7_ADDR_1_HI()
1905 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)  in CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO()  argument
1907 …return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MA…  in CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO()
1913 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)  in CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI()  argument
1915 …return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MA…  in CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI()
1923 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)  in CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN()  argument
1925 …return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__…  in CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN()
1933 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)  in CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO()  argument
1935 …return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MA…  in CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO()
1941 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)  in CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI()  argument
1943 …return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MA…  in CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI()
1953 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)  in CP_PERFCOUNTER_ACTION_1_ADDR_0_LO()  argument
1955 …return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MA…  in CP_PERFCOUNTER_ACTION_1_ADDR_0_LO()
1961 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)  in CP_PERFCOUNTER_ACTION_2_ADDR_0_HI()  argument
1963 …return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MA…  in CP_PERFCOUNTER_ACTION_2_ADDR_0_HI()
1969 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)  in CP_EVENT_WRITE_0_EVENT()  argument
1971 	return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;  in CP_EVENT_WRITE_0_EVENT()
1979 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)  in CP_EVENT_WRITE_1_ADDR_0_LO()  argument
1981 	return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;  in CP_EVENT_WRITE_1_ADDR_0_LO()
1987 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)  in CP_EVENT_WRITE_2_ADDR_0_HI()  argument
1989 	return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;  in CP_EVENT_WRITE_2_ADDR_0_HI()
1997 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)  in CP_BLIT_0_OP()  argument
1999 	return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;  in CP_BLIT_0_OP()
2005 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)  in CP_BLIT_1_SRC_X1()  argument
2007 	return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;  in CP_BLIT_1_SRC_X1()
2011 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)  in CP_BLIT_1_SRC_Y1()  argument
2013 	return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;  in CP_BLIT_1_SRC_Y1()
2019 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)  in CP_BLIT_2_SRC_X2()  argument
2021 	return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;  in CP_BLIT_2_SRC_X2()
2025 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)  in CP_BLIT_2_SRC_Y2()  argument
2027 	return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;  in CP_BLIT_2_SRC_Y2()
2033 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)  in CP_BLIT_3_DST_X1()  argument
2035 	return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;  in CP_BLIT_3_DST_X1()
2039 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)  in CP_BLIT_3_DST_Y1()  argument
2041 	return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;  in CP_BLIT_3_DST_Y1()
2047 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)  in CP_BLIT_4_DST_X2()  argument
2049 	return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;  in CP_BLIT_4_DST_X2()
2053 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)  in CP_BLIT_4_DST_Y2()  argument
2055 	return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;  in CP_BLIT_4_DST_Y2()
2063 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)  in CP_EXEC_CS_1_NGROUPS_X()  argument
2065 	return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;  in CP_EXEC_CS_1_NGROUPS_X()
2071 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)  in CP_EXEC_CS_2_NGROUPS_Y()  argument
2073 	return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;  in CP_EXEC_CS_2_NGROUPS_Y()
2079 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)  in CP_EXEC_CS_3_NGROUPS_Z()  argument
2081 	return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;  in CP_EXEC_CS_3_NGROUPS_Z()
2090 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_1_ADDR()  argument
2092 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;  in A4XX_CP_EXEC_CS_INDIRECT_1_ADDR()
2098 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX()  argument
2100 …return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALS…  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX()
2104 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY()  argument
2106 …return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALS…  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY()
2110 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ()  argument
2112 …return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALS…  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ()
2119 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO()  argument
2121 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__…  in A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO()
2127 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI()  argument
2129 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__…  in A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI()
2135 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX()  argument
2137 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALS…  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX()
2141 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY()  argument
2143 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALS…  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY()
2147 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ()  argument
2149 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALS…  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ()
2155 static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val)  in A6XX_CP_SET_MARKER_0_MODE()  argument
2157 	return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK;  in A6XX_CP_SET_MARKER_0_MODE()
2161 static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val)  in A6XX_CP_SET_MARKER_0_MARKER()  argument
2163 	return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK;  in A6XX_CP_SET_MARKER_0_MARKER()
2171 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)  in A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG()  argument
2173 …return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_R…  in A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG()
2179 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)  in A6XX_CP_SET_PSEUDO_REG__1_LO()  argument
2181 	return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK;  in A6XX_CP_SET_PSEUDO_REG__1_LO()
2187 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)  in A6XX_CP_SET_PSEUDO_REG__2_HI()  argument
2189 	return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK;  in A6XX_CP_SET_PSEUDO_REG__2_HI()
2195 static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val)  in A6XX_CP_REG_TEST_0_REG()  argument
2197 	return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK;  in A6XX_CP_REG_TEST_0_REG()
2201 static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)  in A6XX_CP_REG_TEST_0_BIT()  argument
2203 	return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK;  in A6XX_CP_REG_TEST_0_BIT()
2210 static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val)  in CP_COND_REG_EXEC_0_REG0()  argument
2212 	return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK;  in CP_COND_REG_EXEC_0_REG0()
2219 static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)  in CP_COND_REG_EXEC_0_MODE()  argument
2221 	return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK;  in CP_COND_REG_EXEC_0_MODE()
2227 static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val)  in CP_COND_REG_EXEC_1_DWORDS()  argument
2229 	return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK;  in CP_COND_REG_EXEC_1_DWORDS()
2235 static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val)  in CP_COND_EXEC_0_ADDR0_LO()  argument
2237 	return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK;  in CP_COND_EXEC_0_ADDR0_LO()
2243 static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val)  in CP_COND_EXEC_1_ADDR0_HI()  argument
2245 	return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK;  in CP_COND_EXEC_1_ADDR0_HI()
2251 static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val)  in CP_COND_EXEC_2_ADDR1_LO()  argument
2253 	return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK;  in CP_COND_EXEC_2_ADDR1_LO()
2259 static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val)  in CP_COND_EXEC_3_ADDR1_HI()  argument
2261 	return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK;  in CP_COND_EXEC_3_ADDR1_HI()
2267 static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val)  in CP_COND_EXEC_4_REF()  argument
2269 	return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK;  in CP_COND_EXEC_4_REF()
2275 static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val)  in CP_COND_EXEC_5_DWORDS()  argument
2277 	return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK;  in CP_COND_EXEC_5_DWORDS()
2283 static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)  in CP_SET_CTXSWITCH_IB_0_ADDR_LO()  argument
2285 	return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK;  in CP_SET_CTXSWITCH_IB_0_ADDR_LO()
2291 static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)  in CP_SET_CTXSWITCH_IB_1_ADDR_HI()  argument
2293 	return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK;  in CP_SET_CTXSWITCH_IB_1_ADDR_HI()
2299 static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)  in CP_SET_CTXSWITCH_IB_2_DWORDS()  argument
2301 	return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK;  in CP_SET_CTXSWITCH_IB_2_DWORDS()
2305 static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)  in CP_SET_CTXSWITCH_IB_2_TYPE()  argument
2307 	return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK;  in CP_SET_CTXSWITCH_IB_2_TYPE()
2313 static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)  in CP_REG_WRITE_0_TRACKER()  argument
2315 	return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK;  in CP_REG_WRITE_0_TRACKER()
2321 static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)  in CP_SMMU_TABLE_UPDATE_0_TTBR0_LO()  argument
2323 	return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK;  in CP_SMMU_TABLE_UPDATE_0_TTBR0_LO()
2329 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)  in CP_SMMU_TABLE_UPDATE_1_TTBR0_HI()  argument
2331 	return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK;  in CP_SMMU_TABLE_UPDATE_1_TTBR0_HI()
2335 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)  in CP_SMMU_TABLE_UPDATE_1_ASID()  argument
2337 	return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK;  in CP_SMMU_TABLE_UPDATE_1_ASID()
2343 static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)  in CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR()  argument
2345 …return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MA…  in CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR()
2351 static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)  in CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK()  argument
2353 …return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__…  in CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK()