126 	void		(*top_write)(struct meson_dw_hdmi *dw_hdmi,  member
218 	dw_hdmi->data->top_write(dw_hdmi, addr, data);  in dw_hdmi_top_write_bits()
394 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_SW_RESET,  0);  in dw_hdmi_phy_init()
405 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));  in dw_hdmi_phy_init()
409 		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,  in dw_hdmi_phy_init()
411 		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,  in dw_hdmi_phy_init()
414 		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,  in dw_hdmi_phy_init()
416 		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,  in dw_hdmi_phy_init()
421 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);  in dw_hdmi_phy_init()
423 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);  in dw_hdmi_phy_init()
513 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_HPD_FILTER,  in dw_hdmi_setup_hpd()
517 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,  in dw_hdmi_setup_hpd()
539 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, stat);  in dw_hdmi_top_irq()
615 	.top_write = dw_hdmi_top_write,
622 	.top_write = dw_hdmi_g12a_top_write,
651 	meson_dw_hdmi->data->top_write(meson_dw_hdmi,  in meson_dw_hdmi_init()
656 	meson_dw_hdmi->data->top_write(meson_dw_hdmi,  in meson_dw_hdmi_init()
660 	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,  in meson_dw_hdmi_init()
663 	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN,  in meson_dw_hdmi_init()
847 	meson_dw_hdmi->data->top_write(meson_dw_hdmi,  in meson_dw_hdmi_pm_suspend()