Lines Matching refs:_MMIO

25 #define CTG_STOLEN_RESERVED			_MMIO(MCHBAR_MIRROR_BASE + 0x34)
26 #define ELK_STOLEN_RESERVED			_MMIO(MCHBAR_MIRROR_BASE + 0x48)
32 #define CSHRDDR3CTL				_MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
36 #define DCC					_MMIO(MCHBAR_MIRROR_BASE + 0x200)
43 #define DCC2					_MMIO(MCHBAR_MIRROR_BASE + 0x204)
47 #define C0DRB3_BW				_MMIO(MCHBAR_MIRROR_BASE + 0x206)
48 #define C1DRB3_BW				_MMIO(MCHBAR_MIRROR_BASE + 0x606)
51 #define CLKCFG					_MMIO(MCHBAR_MIRROR_BASE + 0xc00)
68 #define HPLLVCO_MOBILE				_MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
69 #define HPLLVCO					_MMIO(MCHBAR_MIRROR_BASE + 0xc38)
71 #define TSC1					_MMIO(MCHBAR_MIRROR_BASE + 0x1001)
73 #define TR1					_MMIO(MCHBAR_MIRROR_BASE + 0x1006)
74 #define TSFS					_MMIO(MCHBAR_MIRROR_BASE + 0x1020)
80 #define MLTR_ILK				_MMIO(MCHBAR_MIRROR_BASE + 0x1222)
85 #define CSIPLL0					_MMIO(MCHBAR_MIRROR_BASE + 0x2c10)
86 #define DDRMPLL1				_MMIO(MCHBAR_MIRROR_BASE + 0x2c20)
88 #define ILK_GDSR				_MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
99 #define BXT_D_CR_DRP0_DUNIT(x)			_MMIO(MCHBAR_MIRROR_BASE_SNB + \
125 #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
128 #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
132 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
140 #define MAD_DIMM_C0				_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
141 #define MAD_DIMM_C1				_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
142 #define MAD_DIMM_C2				_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
161 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
162 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
188 #define SA_PERF_STATUS_0_0_0_MCHBAR_PC		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
192 #define GEN6_GT_PERF_STATUS			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
193 #define GEN6_RP_STATE_LIMITS			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
194 #define GEN6_RP_STATE_CAP			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
200 #define MCH_SSKPD				_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
213 #define DCLK					_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
214 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
221 #define D_COMP_HSW				_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5f0c)
226 #define BXT_GT_PERF_STATUS			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)