Lines Matching refs:_MMIO
71 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
72 (_MMIO(0x50090))) : \
73 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
74 (_MMIO(0x50098))) : \
75 (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
76 (_MMIO(0x5009C))) : \
77 (_MMIO(0x50080))))); })
117 #define PCH_GPIO_BASE _MMIO(0xc5010)
119 #define PCH_GMBUS0 _MMIO(0xc5100)
120 #define PCH_GMBUS1 _MMIO(0xc5104)
121 #define PCH_GMBUS2 _MMIO(0xc5108)
122 #define PCH_GMBUS3 _MMIO(0xc510c)
123 #define PCH_GMBUS4 _MMIO(0xc5110)
124 #define PCH_GMBUS5 _MMIO(0xc5120)
126 #define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i) * 4)
127 #define TRNULLDETCT _MMIO(0x4de8)
128 #define TRINVTILEDETCT _MMIO(0x4dec)
129 #define TRVADR _MMIO(0x4df0)
130 #define TRTTE _MMIO(0x4df4)
131 #define RING_EXCC(base) _MMIO((base) + 0x28)
132 #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
133 #define VF_GUARDBAND _MMIO(0x83a4)
138 #define PCH_PP_STATUS _MMIO(0xc7200)
139 #define PCH_PP_CONTROL _MMIO(0xc7204)
140 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
141 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
142 #define PCH_PP_DIVISOR _MMIO(0xc7210)