Lines Matching refs:transcoder
119 enum transcoder trans_shift; in psr_irq_control()
130 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); in psr_irq_control()
132 trans_shift = intel_dp->psr.transcoder; in psr_irq_control()
188 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_irq_handler()
191 enum transcoder trans_shift; in intel_psr_irq_handler()
196 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); in intel_psr_irq_handler()
198 trans_shift = intel_dp->psr.transcoder; in intel_psr_irq_handler()
479 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & in hsw_activate_psr1()
481 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); in hsw_activate_psr1()
576 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); in hsw_activate_psr2()
580 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); in hsw_activate_psr2()
587 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); in hsw_activate_psr2()
589 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); in hsw_activate_psr2()
593 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) in transcoder_has_psr2()
619 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); in psr2_program_idle_frames()
622 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); in psr2_program_idle_frames()
1037 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); in intel_psr_get_config()
1043 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder)); in intel_psr_get_config()
1054 enum transcoder transcoder = intel_dp->psr.transcoder; in intel_psr_activate() local
1056 if (transcoder_has_psr2(dev_priv, transcoder)) in intel_psr_activate()
1058 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE); in intel_psr_activate()
1061 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE); in intel_psr_activate()
1093 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_enable_source()
1110 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), in intel_psr_enable_source()
1152 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), in intel_psr_enable_source()
1192 TRANS_PSR_IIR(intel_dp->psr.transcoder)); in psr_interrupt_error_check()
1196 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder); in psr_interrupt_error_check()
1222 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; in intel_psr_enable_locked()
1253 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { in intel_psr_exit()
1255 EDP_PSR2_CTL(intel_dp->psr.transcoder)); in intel_psr_exit()
1260 EDP_PSR_CTL(intel_dp->psr.transcoder)); in intel_psr_exit()
1269 EDP_PSR2_CTL(intel_dp->psr.transcoder)); in intel_psr_exit()
1273 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); in intel_psr_exit()
1276 EDP_PSR_CTL(intel_dp->psr.transcoder)); in intel_psr_exit()
1280 EDP_PSR_CTL(intel_dp->psr.transcoder), val); in intel_psr_exit()
1292 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); in intel_psr_wait_exit_locked()
1295 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); in intel_psr_wait_exit_locked()
1332 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), in intel_psr_disable_locked()
1479 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), in psr_force_hw_tracking_exit()
1928 EDP_PSR2_STATUS(intel_dp->psr.transcoder), in _psr2_ready_for_pipe_update_locked()
1943 EDP_PSR_STATUS(intel_dp->psr.transcoder), in _psr1_ready_for_pipe_update_locked()
1993 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); in __psr_wait_for_idle_locked()
1996 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); in __psr_wait_for_idle_locked()
2168 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val); in _psr_invalidate_handle()
2260 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), in _psr_flush_handle()