302 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)  in dsi_write()  function
380 	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(16)  in dw_mipi_message_config()
388 	dsi_write(dsi, DSI_CMD_MODE_CFG, val);  in dw_mipi_message_config()
395 	dsi_write(dsi, DSI_VID_MODE_CFG, val);  in dw_mipi_message_config()
411 	dsi_write(dsi, DSI_GEN_HDR, hdr_val);  in dw_mipi_dsi_gen_pkt_hdr_write()
437 			dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));  in dw_mipi_dsi_write()
441 			dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));  in dw_mipi_dsi_write()
566 	dsi_write(dsi, DSI_VID_MODE_CFG, val);  in dw_mipi_dsi_video_mode_config()
574 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_set_mode()
577 		dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);  in dw_mipi_dsi_set_mode()
580 		dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);  in dw_mipi_dsi_set_mode()
586 	dsi_write(dsi, DSI_LPCLK_CTRL, val);  in dw_mipi_dsi_set_mode()
588 	dsi_write(dsi, DSI_PWR_UP, POWERUP);  in dw_mipi_dsi_set_mode()
593 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_disable()
594 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);  in dw_mipi_dsi_disable()
624 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_init()
631 	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |  in dw_mipi_dsi_init()
660 	dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));  in dw_mipi_dsi_dpi_config()
661 	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);  in dw_mipi_dsi_dpi_config()
662 	dsi_write(dsi, DSI_DPI_CFG_POL, val);  in dw_mipi_dsi_dpi_config()
667 	dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);  in dw_mipi_dsi_packet_handler_config()
681 	dsi_write(dsi, DSI_VID_PKT_SIZE,  in dw_mipi_dsi_video_packet_config()
694 	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));  in dw_mipi_dsi_command_mode_config()
700 	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);  in dw_mipi_dsi_command_mode_config()
701 	dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);  in dw_mipi_dsi_command_mode_config()
735 	dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
738 	dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
741 	dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
754 	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);  in dw_mipi_dsi_vertical_timing_config()
755 	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);  in dw_mipi_dsi_vertical_timing_config()
756 	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);  in dw_mipi_dsi_vertical_timing_config()
757 	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);  in dw_mipi_dsi_vertical_timing_config()
783 		dsi_write(dsi, DSI_PHY_TMR_CFG,  in dw_mipi_dsi_dphy_timing_config()
786 		dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));  in dw_mipi_dsi_dphy_timing_config()
788 		dsi_write(dsi, DSI_PHY_TMR_CFG,  in dw_mipi_dsi_dphy_timing_config()
794 	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,  in dw_mipi_dsi_dphy_timing_config()
806 	dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |  in dw_mipi_dsi_dphy_interface_config()
813 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK  in dw_mipi_dsi_dphy_init()
815 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);  in dw_mipi_dsi_dphy_init()
816 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);  in dw_mipi_dsi_dphy_init()
817 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);  in dw_mipi_dsi_dphy_init()
825 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |  in dw_mipi_dsi_dphy_enable()
844 	dsi_write(dsi, DSI_INT_MSK0, 0);  in dw_mipi_dsi_clear_err()
845 	dsi_write(dsi, DSI_INT_MSK1, 0);  in dw_mipi_dsi_clear_err()
1036 	dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg);  in dw_mipi_dsi_debugfs_write()