Lines Matching refs:AST_IO_CRTC_PORT
224 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4)); in ast_set_vbios_color_reg()
226 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); in ast_set_vbios_color_reg()
229 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); in ast_set_vbios_color_reg()
230 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8); in ast_set_vbios_color_reg()
243 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); in ast_set_vbios_mode_reg()
244 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); in ast_set_vbios_mode_reg()
246 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); in ast_set_vbios_mode_reg()
249 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); in ast_set_vbios_mode_reg()
250 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); in ast_set_vbios_mode_reg()
251 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); in ast_set_vbios_mode_reg()
252 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); in ast_set_vbios_mode_reg()
253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); in ast_set_vbios_mode_reg()
254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); in ast_set_vbios_mode_reg()
280 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); in ast_set_std_reg()
282 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); in ast_set_std_reg()
284 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); in ast_set_std_reg()
286 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); in ast_set_std_reg()
317 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); in ast_set_crtc_reg()
322 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); in ast_set_crtc_reg()
327 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); in ast_set_crtc_reg()
332 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); in ast_set_crtc_reg()
339 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); in ast_set_crtc_reg()
344 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); in ast_set_crtc_reg()
349 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); in ast_set_crtc_reg()
351 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); in ast_set_crtc_reg()
352 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); in ast_set_crtc_reg()
362 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); in ast_set_crtc_reg()
371 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); in ast_set_crtc_reg()
378 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); in ast_set_crtc_reg()
387 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); in ast_set_crtc_reg()
396 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); in ast_set_crtc_reg()
401 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); in ast_set_crtc_reg()
403 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); in ast_set_crtc_reg()
404 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); in ast_set_crtc_reg()
405 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); in ast_set_crtc_reg()
408 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80); in ast_set_crtc_reg()
410 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00); in ast_set_crtc_reg()
412 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); in ast_set_crtc_reg()
421 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); in ast_set_offset_reg()
422 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); in ast_set_offset_reg()
436 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); in ast_set_dclk_reg()
437 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); in ast_set_dclk_reg()
438 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, in ast_set_dclk_reg()
467 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); in ast_set_color_reg()
468 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); in ast_set_color_reg()
469 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); in ast_set_color_reg()
476 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0xe0); in ast_set_crtthd_reg()
477 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0xa0); in ast_set_crtthd_reg()
480 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); in ast_set_crtthd_reg()
481 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); in ast_set_crtthd_reg()
486 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); in ast_set_crtthd_reg()
487 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); in ast_set_crtthd_reg()
489 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); in ast_set_crtthd_reg()
490 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); in ast_set_crtthd_reg()
515 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); in ast_set_start_address_crt1()
516 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); in ast_set_start_address_crt1()
517 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); in ast_set_start_address_crt1()
727 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0); in ast_set_cursor_base()
728 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1); in ast_set_cursor_base()
729 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2); in ast_set_cursor_base()
740 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); in ast_set_cursor_location()
741 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); in ast_set_cursor_location()
742 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, x0); in ast_set_cursor_location()
743 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, x1); in ast_set_cursor_location()
744 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, y0); in ast_set_cursor_location()
745 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, y1); in ast_set_cursor_location()
758 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, mask, vgacrcb); in ast_set_cursor_enabled()
999 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xfc, 0); in ast_crtc_dpms()
1024 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xfc, ch); in ast_crtc_dpms()
1055 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); in ast_crtc_helper_mode_valid()
1177 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); in ast_crtc_helper_atomic_enable()