116 #define DCCG_REG_FIELD_LIST(type) \  argument
117 	type DPPCLK0_DTO_PHASE;\
118 	type DPPCLK0_DTO_MODULO;\
119 	type DPPCLK_DTO_ENABLE[6];\
120 	type DPPCLK_DTO_DB_EN[6];\
121 	type REFCLK_CLOCK_EN;\
122 	type REFCLK_SRC_SEL;\
123 	type DISPCLK_STEP_DELAY;\
124 	type DISPCLK_STEP_SIZE;\
125 	type DISPCLK_FREQ_RAMP_DONE;\
126 	type DISPCLK_MAX_ERRDET_CYCLES;\
127 	type DCCG_FIFO_ERRDET_RESET;\
128 	type DCCG_FIFO_ERRDET_STATE;\
129 	type DCCG_FIFO_ERRDET_OVR_EN;\
130 	type DISPCLK_CHG_FWD_CORR_DISABLE;\
131 	type DISPCLK_FREQ_CHANGE_CNTL;\
132 	type OTG_ADD_PIXEL[MAX_PIPES];\
133 	type OTG_DROP_PIXEL[MAX_PIPES];
135 #define DCCG3_REG_FIELD_LIST(type) \  argument
136 	type PHYASYMCLK_FORCE_EN;\
137 	type PHYASYMCLK_FORCE_SRC_SEL;\
138 	type PHYBSYMCLK_FORCE_EN;\
139 	type PHYBSYMCLK_FORCE_SRC_SEL;\
140 	type PHYCSYMCLK_FORCE_EN;\
141 	type PHYCSYMCLK_FORCE_SRC_SEL;
143 #define DCCG31_REG_FIELD_LIST(type) \  argument
144 	type PHYDSYMCLK_FORCE_EN;\
145 	type PHYDSYMCLK_FORCE_SRC_SEL;\
146 	type PHYESYMCLK_FORCE_EN;\
147 	type PHYESYMCLK_FORCE_SRC_SEL;\
148 	type DPSTREAMCLK_PIPE0_EN;\
149 	type DPSTREAMCLK_PIPE1_EN;\
150 	type DPSTREAMCLK_PIPE2_EN;\
151 	type DPSTREAMCLK_PIPE3_EN;\
152 	type HDMISTREAMCLK0_SRC_SEL;\
153 	type HDMISTREAMCLK0_DTO_FORCE_DIS;\
154 	type SYMCLK32_SE0_SRC_SEL;\
155 	type SYMCLK32_SE1_SRC_SEL;\
156 	type SYMCLK32_SE2_SRC_SEL;\
157 	type SYMCLK32_SE3_SRC_SEL;\
158 	type SYMCLK32_SE0_EN;\
159 	type SYMCLK32_SE1_EN;\
160 	type SYMCLK32_SE2_EN;\
161 	type SYMCLK32_SE3_EN;\
162 	type SYMCLK32_LE0_SRC_SEL;\
163 	type SYMCLK32_LE1_SRC_SEL;\
164 	type SYMCLK32_LE0_EN;\
165 	type SYMCLK32_LE1_EN;\
166 	type DTBCLK_DTO_ENABLE[MAX_PIPES];\
167 	type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
168 	type PIPE_DTO_SRC_SEL[MAX_PIPES];\
169 	type DTBCLK_DTO_DIV[MAX_PIPES];\
170 	type DCCG_AUDIO_DTO_SEL;\
171 	type DCCG_AUDIO_DTO0_SOURCE_SEL;\
172 	type DENTIST_DISPCLK_CHG_MODE;\
173 	type DSCCLK0_DTO_PHASE;\
174 	type DSCCLK0_DTO_MODULO;\
175 	type DSCCLK1_DTO_PHASE;\
176 	type DSCCLK1_DTO_MODULO;\
177 	type DSCCLK2_DTO_PHASE;\
178 	type DSCCLK2_DTO_MODULO;\
179 	type DSCCLK0_DTO_ENABLE;\
180 	type DSCCLK1_DTO_ENABLE;\
181 	type DSCCLK2_DTO_ENABLE;\
182 	type SYMCLK32_ROOT_SE0_GATE_DISABLE;\
183 	type SYMCLK32_ROOT_SE1_GATE_DISABLE;\
184 	type SYMCLK32_ROOT_SE2_GATE_DISABLE;\
185 	type SYMCLK32_ROOT_SE3_GATE_DISABLE;\
186 	type SYMCLK32_SE0_GATE_DISABLE;\
187 	type SYMCLK32_SE1_GATE_DISABLE;\
188 	type SYMCLK32_SE2_GATE_DISABLE;\
189 	type SYMCLK32_SE3_GATE_DISABLE;\
190 	type SYMCLK32_ROOT_LE0_GATE_DISABLE;\
191 	type SYMCLK32_ROOT_LE1_GATE_DISABLE;\
192 	type SYMCLK32_LE0_GATE_DISABLE;\
193 	type SYMCLK32_LE1_GATE_DISABLE;\
194 	type DPSTREAMCLK_ROOT_GATE_DISABLE;\
195 	type DPSTREAMCLK_GATE_DISABLE;\
196 	type HDMISTREAMCLK0_DTO_PHASE;\
197 	type HDMISTREAMCLK0_DTO_MODULO;\
198 	type HDMICHARCLK0_GATE_DISABLE;\
199 	type HDMICHARCLK0_ROOT_GATE_DISABLE; \
200 	type PHYASYMCLK_GATE_DISABLE; \
201 	type PHYBSYMCLK_GATE_DISABLE; \
202 	type PHYCSYMCLK_GATE_DISABLE; \
203 	type PHYDSYMCLK_GATE_DISABLE; \
204 	type PHYESYMCLK_GATE_DISABLE;