Lines Matching refs:type
226 #define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \ argument
227 type DIG_ENABLE;\
228 type DIG_HPD_SELECT;\
229 type DIG_MODE;\
230 type DIG_FE_SOURCE_SELECT;\
231 type DIG_CLOCK_PATTERN;\
232 type DPHY_BYPASS;\
233 type DPHY_ATEST_SEL_LANE0;\
234 type DPHY_ATEST_SEL_LANE1;\
235 type DPHY_ATEST_SEL_LANE2;\
236 type DPHY_ATEST_SEL_LANE3;\
237 type DPHY_PRBS_EN;\
238 type DPHY_PRBS_SEL;\
239 type DPHY_SYM1;\
240 type DPHY_SYM2;\
241 type DPHY_SYM3;\
242 type DPHY_SYM4;\
243 type DPHY_SYM5;\
244 type DPHY_SYM6;\
245 type DPHY_SYM7;\
246 type DPHY_SYM8;\
247 type DPHY_SCRAMBLER_BS_COUNT;\
248 type DPHY_SCRAMBLER_ADVANCE;\
249 type DPHY_RX_FAST_TRAINING_CAPABLE;\
250 type DPHY_LOAD_BS_COUNT;\
251 type DPHY_TRAINING_PATTERN_SEL;\
252 type DP_DPHY_HBR2_PATTERN_CONTROL;\
253 type DP_LINK_TRAINING_COMPLETE;\
254 type DP_IDLE_BS_INTERVAL;\
255 type DP_VBID_DISABLE;\
256 type DP_VID_ENHANCED_FRAME_MODE;\
257 type DP_VID_STREAM_ENABLE;\
258 type DP_UDI_LANES;\
259 type DP_SEC_GSP0_LINE_NUM;\
260 type DP_SEC_GSP0_PRIORITY;\
261 type DP_MSE_SAT_SRC0;\
262 type DP_MSE_SAT_SRC1;\
263 type DP_MSE_SAT_SRC2;\
264 type DP_MSE_SAT_SRC3;\
265 type DP_MSE_SAT_SLOT_COUNT0;\
266 type DP_MSE_SAT_SLOT_COUNT1;\
267 type DP_MSE_SAT_SLOT_COUNT2;\
268 type DP_MSE_SAT_SLOT_COUNT3;\
269 type DP_MSE_SAT_UPDATE;\
270 type DP_MSE_16_MTP_KEEPOUT;\
271 type DC_HPD_EN;\
272 type TMDS_CTL0;\
273 type AUX_HPD_SEL;\
274 type AUX_LS_READ_EN;\
275 type AUX_RX_RECEIVE_WINDOW
278 #define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \ argument
279 type RDPCS_PHY_DP_TX0_DATA_EN;\
280 type RDPCS_PHY_DP_TX1_DATA_EN;\
281 type RDPCS_PHY_DP_TX2_DATA_EN;\
282 type RDPCS_PHY_DP_TX3_DATA_EN;\
283 type RDPCS_PHY_DP_TX0_PSTATE;\
284 type RDPCS_PHY_DP_TX1_PSTATE;\
285 type RDPCS_PHY_DP_TX2_PSTATE;\
286 type RDPCS_PHY_DP_TX3_PSTATE;\
287 type RDPCS_PHY_DP_TX0_MPLL_EN;\
288 type RDPCS_PHY_DP_TX1_MPLL_EN;\
289 type RDPCS_PHY_DP_TX2_MPLL_EN;\
290 type RDPCS_PHY_DP_TX3_MPLL_EN;\
291 type RDPCS_TX_FIFO_LANE0_EN;\
292 type RDPCS_TX_FIFO_LANE1_EN;\
293 type RDPCS_TX_FIFO_LANE2_EN;\
294 type RDPCS_TX_FIFO_LANE3_EN;\
295 type RDPCS_EXT_REFCLK_EN;\
296 type RDPCS_TX_FIFO_EN;\
297 type UNIPHY_LINK_ENABLE;\
298 type UNIPHY_CHANNEL0_XBAR_SOURCE;\
299 type UNIPHY_CHANNEL1_XBAR_SOURCE;\
300 type UNIPHY_CHANNEL2_XBAR_SOURCE;\
301 type UNIPHY_CHANNEL3_XBAR_SOURCE;\
302 type UNIPHY_CHANNEL0_INVERT;\
303 type UNIPHY_CHANNEL1_INVERT;\
304 type UNIPHY_CHANNEL2_INVERT;\
305 type UNIPHY_CHANNEL3_INVERT;\
306 type UNIPHY_LINK_ENABLE_HPD_MASK;\
307 type UNIPHY_LANE_STAGGER_DELAY;\
308 type RDPCS_SRAMCLK_BYPASS;\
309 type RDPCS_SRAMCLK_EN;\
310 type RDPCS_SRAMCLK_CLOCK_ON;\
311 type DPCS_TX_FIFO_EN;\
312 type RDPCS_PHY_DP_TX0_DISABLE;\
313 type RDPCS_PHY_DP_TX1_DISABLE;\
314 type RDPCS_PHY_DP_TX2_DISABLE;\
315 type RDPCS_PHY_DP_TX3_DISABLE;\
316 type RDPCS_PHY_DP_TX0_CLK_RDY;\
317 type RDPCS_PHY_DP_TX1_CLK_RDY;\
318 type RDPCS_PHY_DP_TX2_CLK_RDY;\
319 type RDPCS_PHY_DP_TX3_CLK_RDY;\
320 type RDPCS_PHY_DP_TX0_REQ;\
321 type RDPCS_PHY_DP_TX1_REQ;\
322 type RDPCS_PHY_DP_TX2_REQ;\
323 type RDPCS_PHY_DP_TX3_REQ;\
324 type RDPCS_PHY_DP_TX0_ACK;\
325 type RDPCS_PHY_DP_TX1_ACK;\
326 type RDPCS_PHY_DP_TX2_ACK;\
327 type RDPCS_PHY_DP_TX3_ACK;\
328 type RDPCS_PHY_DP_TX0_RESET;\
329 type RDPCS_PHY_DP_TX1_RESET;\
330 type RDPCS_PHY_DP_TX2_RESET;\
331 type RDPCS_PHY_DP_TX3_RESET;\
332 type RDPCS_PHY_RESET;\
333 type RDPCS_PHY_CR_MUX_SEL;\
334 type RDPCS_PHY_REF_RANGE;\
335 type RDPCS_PHY_DP4_POR;\
336 type RDPCS_SRAM_BYPASS;\
337 type RDPCS_SRAM_EXT_LD_DONE;\
338 type RDPCS_PHY_DP_TX0_TERM_CTRL;\
339 type RDPCS_PHY_DP_TX1_TERM_CTRL;\
340 type RDPCS_PHY_DP_TX2_TERM_CTRL;\
341 type RDPCS_PHY_DP_TX3_TERM_CTRL;\
342 type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\
343 type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\
344 type RDPCS_PHY_DP_MPLLB_SSC_EN;\
345 type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\
346 type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\
347 type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\
348 type RDPCS_PHY_DP_MPLLB_FRACN_EN;\
349 type RDPCS_PHY_DP_MPLLB_PMIX_EN;\
350 type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\
351 type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\
352 type RDPCS_PHY_DP_MPLLB_FRACN_REM;\
353 type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\
354 type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\
355 type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\
356 type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\
357 type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\
358 type RDPCS_PHY_TX_VBOOST_LVL;\
359 type RDPCS_PHY_HDMIMODE_ENABLE;\
360 type RDPCS_PHY_DP_REF_CLK_EN;\
361 type RDPCS_PLL_UPDATE_DATA;\
362 type RDPCS_SRAM_INIT_DONE;\
363 type RDPCS_TX_CR_ADDR;\
364 type RDPCS_TX_CR_DATA;\
365 type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\
366 type RDPCS_PHY_DP_MPLLB_STATE;\
367 type RDPCS_PHY_DP_TX0_WIDTH;\
368 type RDPCS_PHY_DP_TX0_RATE;\
369 type RDPCS_PHY_DP_TX1_WIDTH;\
370 type RDPCS_PHY_DP_TX1_RATE;\
371 type RDPCS_PHY_DP_TX2_WIDTH;\
372 type RDPCS_PHY_DP_TX2_RATE;\
373 type RDPCS_PHY_DP_TX3_WIDTH;\
374 type RDPCS_PHY_DP_TX3_RATE;\
375 type DPCS_SYMCLK_CLOCK_ON;\
376 type DPCS_SYMCLK_GATE_DIS;\
377 type DPCS_SYMCLK_EN;\
378 type RDPCS_SYMCLK_DIV2_CLOCK_ON;\
379 type RDPCS_SYMCLK_DIV2_GATE_DIS;\
380 type RDPCS_SYMCLK_DIV2_EN;\
381 type DPCS_TX_DATA_SWAP;\
382 type DPCS_TX_DATA_ORDER_INVERT;\
383 type DPCS_TX_FIFO_RD_START_DELAY;\
384 type RDPCS_TX_FIFO_RD_START_DELAY;\
385 type RDPCS_REG_FIFO_ERROR_MASK;\
386 type RDPCS_TX_FIFO_ERROR_MASK;\
387 type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
388 type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
389 type RDPCS_PHY_DPALT_DP4;\
390 type RDPCS_PHY_DPALT_DISABLE;\
391 type RDPCS_PHY_DPALT_DISABLE_ACK;\
392 type RDPCS_PHY_DP_MPLLB_V2I;\
393 type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
394 type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
395 type RDPCS_PHY_RX_VREF_CTRL;\
396 type RDPCS_PHY_DP_MPLLB_CP_INT;\
397 type RDPCS_PHY_DP_MPLLB_CP_PROP;\
398 type RDPCS_PHY_RX_REF_LD_VAL;\
399 type RDPCS_PHY_RX_VCO_LD_VAL;\
400 type DPCSTX_DEBUG_CONFIG; \
401 type RDPCSTX_DEBUG_CONFIG; \
402 type RDPCS_PHY_DP_TX0_EQ_MAIN;\
403 type RDPCS_PHY_DP_TX0_EQ_PRE;\
404 type RDPCS_PHY_DP_TX0_EQ_POST;\
405 type RDPCS_PHY_DP_TX1_EQ_MAIN;\
406 type RDPCS_PHY_DP_TX1_EQ_PRE;\
407 type RDPCS_PHY_DP_TX1_EQ_POST;\
408 type RDPCS_PHY_DP_TX2_EQ_MAIN;\
409 type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
410 type RDPCS_PHY_DP_TX2_EQ_PRE;\
411 type RDPCS_PHY_DP_TX2_EQ_POST;\
412 type RDPCS_PHY_DP_TX3_EQ_MAIN;\
413 type RDPCS_PHY_DCO_RANGE;\
414 type RDPCS_PHY_DCO_FINETUNE;\
415 type RDPCS_PHY_DP_TX3_EQ_PRE;\
416 type RDPCS_PHY_DP_TX3_EQ_POST;\
417 type RDPCS_PHY_SUP_PRE_HP;\
418 type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
419 type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
420 type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
421 type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
422 type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
423 type UNIPHYA_SOFT_RESET;\
424 type UNIPHYB_SOFT_RESET;\
425 type UNIPHYC_SOFT_RESET;\
426 type UNIPHYD_SOFT_RESET;\
427 type UNIPHYE_SOFT_RESET;\
428 type UNIPHYF_SOFT_RESET
430 #define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \ argument
431 type DIG_LANE0EN;\
432 type DIG_LANE1EN;\
433 type DIG_LANE2EN;\
434 type DIG_LANE3EN;\
435 type DIG_CLK_EN;\
436 type SYMCLKA_CLOCK_ENABLE;\
437 type DPHY_FEC_EN;\
438 type DPHY_FEC_READY_SHADOW;\
439 type DPHY_FEC_ACTIVE_STATUS;\
440 DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\
441 type VCO_LD_VAL_OVRD;\
442 type VCO_LD_VAL_OVRD_EN;\
443 type REF_LD_VAL_OVRD;\
444 type REF_LD_VAL_OVRD_EN;\
445 type AUX_RX_START_WINDOW; \
446 type AUX_RX_HALF_SYM_DETECT_LEN; \
447 type AUX_RX_TRANSITION_FILTER_EN; \
448 type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \
449 type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \
450 type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \
451 type AUX_RX_PHASE_DETECT_LEN; \
452 type AUX_RX_DETECTION_THRESHOLD; \
453 type AUX_TX_PRECHARGE_LEN; \
454 type AUX_TX_PRECHARGE_SYMBOLS; \
455 type AUX_MODE_DET_CHECK_DELAY;\
456 type DPCS_DBG_CBUS_DIS;\
457 type AUX_RX_PRECHARGE_SKIP;\
458 type AUX_RX_TIMEOUT_LEN;\
459 type AUX_RX_TIMEOUT_LEN_MUL
461 #define DCN30_LINK_ENCODER_REG_FIELD_LIST(type) \ argument
462 type TMDS_SYNC_DCBAL_EN;\
463 type PHY_HPO_DIG_SRC_SEL;\
464 type PHY_HPO_ENC_SRC_SEL;\
465 type DPCS_TX_HDMI_FRL_MODE;\
466 type DPCS_TX_DATA_SWAP_10_BIT;\
467 type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\
468 type RDPCS_TX_CLK_EN
470 #define DCN31_LINK_ENCODER_REG_FIELD_LIST(type) \ argument
471 type ENC_TYPE_SEL;\
472 type HPO_DP_ENC_SEL;\
473 type HPO_HDMI_ENC_SEL