28 #define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)  argument
40 #define WREG32_FIELD15(ip, idx, reg, field, val)	\  argument
48 #define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val)        \  argument
56 #define RREG32_SOC15(ip, inst, reg) \  argument
60 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP)  argument
62 #define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP)  argument
64 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \  argument
68 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \  argument
71 #define WREG32_SOC15(ip, inst, reg, value) \  argument
75 #define WREG32_SOC15_IP(ip, reg, value) \  argument
78 #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \  argument
81 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \  argument
85 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \  argument
89 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \  argument
143 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \  argument
156 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \  argument
174 #define RREG32_SOC15_RLC(ip, inst, reg) \  argument
177 #define WREG32_SOC15_RLC(ip, inst, reg, value) \  argument
183 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \  argument
189 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val)   \  argument
196 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \  argument
199 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \  argument