134 	err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);  in gmc_v6_0_init_microcode()
138 	err = amdgpu_ucode_validate(adev->gmc.fw);  in gmc_v6_0_init_microcode()
145 		release_firmware(adev->gmc.fw);  in gmc_v6_0_init_microcode()
146 		adev->gmc.fw = NULL;  in gmc_v6_0_init_microcode()
159 	if (!adev->gmc.fw)  in gmc_v6_0_mc_load_microcode()
162 	hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;  in gmc_v6_0_mc_load_microcode()
166 	adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);  in gmc_v6_0_mc_load_microcode()
169 		(adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));  in gmc_v6_0_mc_load_microcode()
172 		(adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));  in gmc_v6_0_mc_load_microcode()
257 	       adev->gmc.vram_start >> 12);  in gmc_v6_0_mc_program()
259 	       adev->gmc.vram_end >> 12);  in gmc_v6_0_mc_program()
317 	adev->gmc.vram_width = numchan * chansize;  in gmc_v6_0_mc_init()
319 	adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v6_0_mc_init()
320 	adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v6_0_mc_init()
327 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);  in gmc_v6_0_mc_init()
328 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);  in gmc_v6_0_mc_init()
329 	adev->gmc.visible_vram_size = adev->gmc.aper_size;  in gmc_v6_0_mc_init()
336 			adev->gmc.gart_size = 256ULL << 20;  in gmc_v6_0_mc_init()
342 			adev->gmc.gart_size = 1024ULL << 20;  in gmc_v6_0_mc_init()
346 		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;  in gmc_v6_0_mc_init()
349 	adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;  in gmc_v6_0_mc_init()
350 	gmc_v6_0_vram_gtt_location(adev, &adev->gmc);  in gmc_v6_0_mc_init()
424 	if (enable && !adev->gmc.prt_warning) {  in gmc_v6_0_set_prt()
426 		adev->gmc.prt_warning = true;  in gmc_v6_0_set_prt()
509 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);  in gmc_v6_0_gart_enable()
510 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);  in gmc_v6_0_gart_enable()
557 		 (unsigned)(adev->gmc.gart_size >> 20),  in gmc_v6_0_gart_enable()
792 		return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);  in gmc_v6_0_late_init()
821 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;  in gmc_v6_0_sw_init()
825 		adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);  in gmc_v6_0_sw_init()
828 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);  in gmc_v6_0_sw_init()
832 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);  in gmc_v6_0_sw_init()
838 	adev->gmc.mc_mask = 0xffffffffffULL;  in gmc_v6_0_sw_init()
897 	release_firmware(adev->gmc.fw);  in gmc_v6_0_sw_fini()
898 	adev->gmc.fw = NULL;  in gmc_v6_0_sw_fini()
932 	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);  in gmc_v6_0_hw_fini()
1143 	adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;  in gmc_v6_0_set_gmc_funcs()
1148 	adev->gmc.vm_fault.num_types = 1;  in gmc_v6_0_set_irq_funcs()
1149 	adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;  in gmc_v6_0_set_irq_funcs()