35 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
36 		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
37 		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
38 		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
39 		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
40 		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
41 		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
42 		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
43 		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
44 		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
45 		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
46 		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
47 		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
48 		adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
49 		adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
50 		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()
51 		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));  in dimgrey_cavefish_reg_base_init()