1788 	uint32_t fb_format, fb_pitch_pixels;  in dce_v8_0_crtc_do_set_base()  local
1831 		fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v8_0_crtc_do_set_base()
1836 		fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v8_0_crtc_do_set_base()
1844 		fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v8_0_crtc_do_set_base()
1852 		fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v8_0_crtc_do_set_base()
1859 		fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v8_0_crtc_do_set_base()
1867 		fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v8_0_crtc_do_set_base()
1875 		fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v8_0_crtc_do_set_base()
1885 		fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v8_0_crtc_do_set_base()
1895 		fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v8_0_crtc_do_set_base()
1918 		fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);  in dce_v8_0_crtc_do_set_base()
1919 		fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);  in dce_v8_0_crtc_do_set_base()
1920 		fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);  in dce_v8_0_crtc_do_set_base()
1921 		fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);  in dce_v8_0_crtc_do_set_base()
1922 		fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);  in dce_v8_0_crtc_do_set_base()
1923 		fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);  in dce_v8_0_crtc_do_set_base()
1924 		fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);  in dce_v8_0_crtc_do_set_base()
1926 		fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);  in dce_v8_0_crtc_do_set_base()
1929 	fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);  in dce_v8_0_crtc_do_set_base()
1946 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v8_0_crtc_do_set_base()