Lines Matching defs:amdgpu_crtc
374 struct amdgpu_crtc { struct
375 struct drm_crtc base;
376 int crtc_id;
377 bool enabled;
378 bool can_tile;
379 uint32_t crtc_offset;
380 struct drm_gem_object *cursor_bo;
381 uint64_t cursor_addr;
382 int cursor_x;
383 int cursor_y;
384 int cursor_hot_x;
385 int cursor_hot_y;
386 int cursor_width;
387 int cursor_height;
388 int max_cursor_width;
389 int max_cursor_height;
390 enum amdgpu_rmx_type rmx_type;
391 u8 h_border;
392 u8 v_border;
393 fixed20_12 vsc;
394 fixed20_12 hsc;
395 struct drm_display_mode native_mode;
396 u32 pll_id;
398 struct amdgpu_flip_work *pflip_works;
399 enum amdgpu_flip_status pflip_status;
400 int deferred_flip_completion;
402 struct dm_irq_params dm_irq_params;
404 struct amdgpu_atom_ss ss;
405 bool ss_enabled;
406 u32 adjusted_clock;
407 int bpc;
408 u32 pll_reference_div;
409 u32 pll_post_div;
410 u32 pll_flags;
411 struct drm_encoder *encoder;
412 struct drm_connector *connector;
414 u32 line_time;
415 u32 wm_low;
416 u32 wm_high;
417 u32 lb_vblank_lead_lines;
418 struct drm_display_mode hw_mode;
420 struct hrtimer vblank_timer;
421 enum amdgpu_interrupt_state vsync_timer_enabled;
423 int otg_inst;
424 struct drm_pending_vblank_event *event;