52 	struct mlxbf_gpio_state *gs;  in mlxbf_gpio_probe()  local
57 	gs = devm_kzalloc(&pdev->dev, sizeof(*gs), GFP_KERNEL);  in mlxbf_gpio_probe()
58 	if (!gs)  in mlxbf_gpio_probe()
61 	gs->base = devm_platform_ioremap_resource(pdev, 0);  in mlxbf_gpio_probe()
62 	if (IS_ERR(gs->base))  in mlxbf_gpio_probe()
63 		return PTR_ERR(gs->base);  in mlxbf_gpio_probe()
65 	gc = &gs->gc;  in mlxbf_gpio_probe()
67 			 gs->base + MLXBF_GPIO_PIN_STATE,  in mlxbf_gpio_probe()
70 			 gs->base + MLXBF_GPIO_PIN_DIR_O,  in mlxbf_gpio_probe()
71 			 gs->base + MLXBF_GPIO_PIN_DIR_I,  in mlxbf_gpio_probe()
79 	ret = devm_gpiochip_add_data(dev, &gs->gc, gs);  in mlxbf_gpio_probe()
85 	platform_set_drvdata(pdev, gs);  in mlxbf_gpio_probe()
93 	struct mlxbf_gpio_state *gs = platform_get_drvdata(pdev);  in mlxbf_gpio_suspend()  local
95 	gs->csave_regs.scratchpad = readq(gs->base + MLXBF_GPIO_SCRATCHPAD);  in mlxbf_gpio_suspend()
96 	gs->csave_regs.pad_control[0] =  in mlxbf_gpio_suspend()
97 		readq(gs->base + MLXBF_GPIO_PAD_CONTROL_FIRST_WORD);  in mlxbf_gpio_suspend()
98 	gs->csave_regs.pad_control[1] =  in mlxbf_gpio_suspend()
99 		readq(gs->base + MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD);  in mlxbf_gpio_suspend()
100 	gs->csave_regs.pad_control[2] =  in mlxbf_gpio_suspend()
101 		readq(gs->base + MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD);  in mlxbf_gpio_suspend()
102 	gs->csave_regs.pad_control[3] =  in mlxbf_gpio_suspend()
103 		readq(gs->base + MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD);  in mlxbf_gpio_suspend()
104 	gs->csave_regs.pin_dir_i = readq(gs->base + MLXBF_GPIO_PIN_DIR_I);  in mlxbf_gpio_suspend()
105 	gs->csave_regs.pin_dir_o = readq(gs->base + MLXBF_GPIO_PIN_DIR_O);  in mlxbf_gpio_suspend()
112 	struct mlxbf_gpio_state *gs = platform_get_drvdata(pdev);  in mlxbf_gpio_resume()  local
114 	writeq(gs->csave_regs.scratchpad, gs->base + MLXBF_GPIO_SCRATCHPAD);  in mlxbf_gpio_resume()
115 	writeq(gs->csave_regs.pad_control[0],  in mlxbf_gpio_resume()
116 	       gs->base + MLXBF_GPIO_PAD_CONTROL_FIRST_WORD);  in mlxbf_gpio_resume()
117 	writeq(gs->csave_regs.pad_control[1],  in mlxbf_gpio_resume()
118 	       gs->base + MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD);  in mlxbf_gpio_resume()
119 	writeq(gs->csave_regs.pad_control[2],  in mlxbf_gpio_resume()
120 	       gs->base + MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD);  in mlxbf_gpio_resume()
121 	writeq(gs->csave_regs.pad_control[3],  in mlxbf_gpio_resume()
122 	       gs->base + MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD);  in mlxbf_gpio_resume()
123 	writeq(gs->csave_regs.pin_dir_i, gs->base + MLXBF_GPIO_PIN_DIR_I);  in mlxbf_gpio_resume()
124 	writeq(gs->csave_regs.pin_dir_o, gs->base + MLXBF_GPIO_PIN_DIR_O);  in mlxbf_gpio_resume()