Lines Matching refs:tr_req
2862 struct cppi5_tr_type1_t *tr_req = NULL; in udma_prep_slave_sg_tr() local
2891 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_slave_sg_tr()
2905 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false, in udma_prep_slave_sg_tr()
2907 cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT); in udma_prep_slave_sg_tr()
2910 tr_req[tr_idx].addr = sg_addr; in udma_prep_slave_sg_tr()
2911 tr_req[tr_idx].icnt0 = tr0_cnt0; in udma_prep_slave_sg_tr()
2912 tr_req[tr_idx].icnt1 = tr0_cnt1; in udma_prep_slave_sg_tr()
2913 tr_req[tr_idx].dim1 = tr0_cnt0; in udma_prep_slave_sg_tr()
2917 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, in udma_prep_slave_sg_tr()
2920 cppi5_tr_csf_set(&tr_req[tr_idx].flags, in udma_prep_slave_sg_tr()
2923 tr_req[tr_idx].addr = sg_addr + tr0_cnt1 * tr0_cnt0; in udma_prep_slave_sg_tr()
2924 tr_req[tr_idx].icnt0 = tr1_cnt0; in udma_prep_slave_sg_tr()
2925 tr_req[tr_idx].icnt1 = 1; in udma_prep_slave_sg_tr()
2926 tr_req[tr_idx].dim1 = tr1_cnt0; in udma_prep_slave_sg_tr()
2933 cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, in udma_prep_slave_sg_tr()
2946 struct cppi5_tr_type15_t *tr_req = NULL; in udma_prep_slave_sg_triggered_tr() local
3023 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_slave_sg_triggered_tr()
3039 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, false, in udma_prep_slave_sg_triggered_tr()
3041 cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT); in udma_prep_slave_sg_triggered_tr()
3042 cppi5_tr_set_trigger(&tr_req[tr_idx].flags, in udma_prep_slave_sg_triggered_tr()
3048 tr_req[tr_idx].addr = dev_addr; in udma_prep_slave_sg_triggered_tr()
3049 tr_req[tr_idx].icnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3050 tr_req[tr_idx].icnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3051 tr_req[tr_idx].icnt2 = tr0_cnt2; in udma_prep_slave_sg_triggered_tr()
3052 tr_req[tr_idx].icnt3 = tr0_cnt3; in udma_prep_slave_sg_triggered_tr()
3053 tr_req[tr_idx].dim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3055 tr_req[tr_idx].daddr = sg_addr; in udma_prep_slave_sg_triggered_tr()
3056 tr_req[tr_idx].dicnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3057 tr_req[tr_idx].dicnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3058 tr_req[tr_idx].dicnt2 = tr0_cnt2; in udma_prep_slave_sg_triggered_tr()
3059 tr_req[tr_idx].dicnt3 = tr0_cnt3; in udma_prep_slave_sg_triggered_tr()
3060 tr_req[tr_idx].ddim1 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3061 tr_req[tr_idx].ddim2 = trigger_size; in udma_prep_slave_sg_triggered_tr()
3062 tr_req[tr_idx].ddim3 = trigger_size * tr0_cnt2; in udma_prep_slave_sg_triggered_tr()
3064 tr_req[tr_idx].addr = sg_addr; in udma_prep_slave_sg_triggered_tr()
3065 tr_req[tr_idx].icnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3066 tr_req[tr_idx].icnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3067 tr_req[tr_idx].icnt2 = tr0_cnt2; in udma_prep_slave_sg_triggered_tr()
3068 tr_req[tr_idx].icnt3 = tr0_cnt3; in udma_prep_slave_sg_triggered_tr()
3069 tr_req[tr_idx].dim1 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3070 tr_req[tr_idx].dim2 = trigger_size; in udma_prep_slave_sg_triggered_tr()
3071 tr_req[tr_idx].dim3 = trigger_size * tr0_cnt2; in udma_prep_slave_sg_triggered_tr()
3073 tr_req[tr_idx].daddr = dev_addr; in udma_prep_slave_sg_triggered_tr()
3074 tr_req[tr_idx].dicnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3075 tr_req[tr_idx].dicnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3076 tr_req[tr_idx].dicnt2 = tr0_cnt2; in udma_prep_slave_sg_triggered_tr()
3077 tr_req[tr_idx].dicnt3 = tr0_cnt3; in udma_prep_slave_sg_triggered_tr()
3078 tr_req[tr_idx].ddim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3084 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, in udma_prep_slave_sg_triggered_tr()
3087 cppi5_tr_csf_set(&tr_req[tr_idx].flags, in udma_prep_slave_sg_triggered_tr()
3089 cppi5_tr_set_trigger(&tr_req[tr_idx].flags, in udma_prep_slave_sg_triggered_tr()
3096 tr_req[tr_idx].addr = dev_addr; in udma_prep_slave_sg_triggered_tr()
3097 tr_req[tr_idx].icnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3098 tr_req[tr_idx].icnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3099 tr_req[tr_idx].icnt2 = tr1_cnt2; in udma_prep_slave_sg_triggered_tr()
3100 tr_req[tr_idx].icnt3 = 1; in udma_prep_slave_sg_triggered_tr()
3101 tr_req[tr_idx].dim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3103 tr_req[tr_idx].daddr = sg_addr; in udma_prep_slave_sg_triggered_tr()
3104 tr_req[tr_idx].dicnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3105 tr_req[tr_idx].dicnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3106 tr_req[tr_idx].dicnt2 = tr1_cnt2; in udma_prep_slave_sg_triggered_tr()
3107 tr_req[tr_idx].dicnt3 = 1; in udma_prep_slave_sg_triggered_tr()
3108 tr_req[tr_idx].ddim1 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3109 tr_req[tr_idx].ddim2 = trigger_size; in udma_prep_slave_sg_triggered_tr()
3111 tr_req[tr_idx].addr = sg_addr; in udma_prep_slave_sg_triggered_tr()
3112 tr_req[tr_idx].icnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3113 tr_req[tr_idx].icnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3114 tr_req[tr_idx].icnt2 = tr1_cnt2; in udma_prep_slave_sg_triggered_tr()
3115 tr_req[tr_idx].icnt3 = 1; in udma_prep_slave_sg_triggered_tr()
3116 tr_req[tr_idx].dim1 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3117 tr_req[tr_idx].dim2 = trigger_size; in udma_prep_slave_sg_triggered_tr()
3119 tr_req[tr_idx].daddr = dev_addr; in udma_prep_slave_sg_triggered_tr()
3120 tr_req[tr_idx].dicnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3121 tr_req[tr_idx].dicnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3122 tr_req[tr_idx].dicnt2 = tr1_cnt2; in udma_prep_slave_sg_triggered_tr()
3123 tr_req[tr_idx].dicnt3 = 1; in udma_prep_slave_sg_triggered_tr()
3124 tr_req[tr_idx].ddim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3132 cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, in udma_prep_slave_sg_triggered_tr()
3452 struct cppi5_tr_type1_t *tr_req; in udma_prep_dma_cyclic_tr() local
3472 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_dma_cyclic_tr()
3482 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false, in udma_prep_dma_cyclic_tr()
3485 tr_req[tr_idx].addr = period_addr; in udma_prep_dma_cyclic_tr()
3486 tr_req[tr_idx].icnt0 = tr0_cnt0; in udma_prep_dma_cyclic_tr()
3487 tr_req[tr_idx].icnt1 = tr0_cnt1; in udma_prep_dma_cyclic_tr()
3488 tr_req[tr_idx].dim1 = tr0_cnt0; in udma_prep_dma_cyclic_tr()
3491 cppi5_tr_csf_set(&tr_req[tr_idx].flags, in udma_prep_dma_cyclic_tr()
3495 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, in udma_prep_dma_cyclic_tr()
3499 tr_req[tr_idx].addr = period_addr + tr0_cnt1 * tr0_cnt0; in udma_prep_dma_cyclic_tr()
3500 tr_req[tr_idx].icnt0 = tr1_cnt0; in udma_prep_dma_cyclic_tr()
3501 tr_req[tr_idx].icnt1 = 1; in udma_prep_dma_cyclic_tr()
3502 tr_req[tr_idx].dim1 = tr1_cnt0; in udma_prep_dma_cyclic_tr()
3506 cppi5_tr_csf_set(&tr_req[tr_idx].flags, in udma_prep_dma_cyclic_tr()
3656 struct cppi5_tr_type15_t *tr_req; in udma_prep_dma_memcpy() local
3692 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_dma_memcpy()
3694 cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true, in udma_prep_dma_memcpy()
3696 cppi5_tr_csf_set(&tr_req[0].flags, CPPI5_TR_CSF_SUPR_EVT); in udma_prep_dma_memcpy()
3698 tr_req[0].addr = src; in udma_prep_dma_memcpy()
3699 tr_req[0].icnt0 = tr0_cnt0; in udma_prep_dma_memcpy()
3700 tr_req[0].icnt1 = tr0_cnt1; in udma_prep_dma_memcpy()
3701 tr_req[0].icnt2 = 1; in udma_prep_dma_memcpy()
3702 tr_req[0].icnt3 = 1; in udma_prep_dma_memcpy()
3703 tr_req[0].dim1 = tr0_cnt0; in udma_prep_dma_memcpy()
3705 tr_req[0].daddr = dest; in udma_prep_dma_memcpy()
3706 tr_req[0].dicnt0 = tr0_cnt0; in udma_prep_dma_memcpy()
3707 tr_req[0].dicnt1 = tr0_cnt1; in udma_prep_dma_memcpy()
3708 tr_req[0].dicnt2 = 1; in udma_prep_dma_memcpy()
3709 tr_req[0].dicnt3 = 1; in udma_prep_dma_memcpy()
3710 tr_req[0].ddim1 = tr0_cnt0; in udma_prep_dma_memcpy()
3713 cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true, in udma_prep_dma_memcpy()
3715 cppi5_tr_csf_set(&tr_req[1].flags, CPPI5_TR_CSF_SUPR_EVT); in udma_prep_dma_memcpy()
3717 tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0; in udma_prep_dma_memcpy()
3718 tr_req[1].icnt0 = tr1_cnt0; in udma_prep_dma_memcpy()
3719 tr_req[1].icnt1 = 1; in udma_prep_dma_memcpy()
3720 tr_req[1].icnt2 = 1; in udma_prep_dma_memcpy()
3721 tr_req[1].icnt3 = 1; in udma_prep_dma_memcpy()
3723 tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0; in udma_prep_dma_memcpy()
3724 tr_req[1].dicnt0 = tr1_cnt0; in udma_prep_dma_memcpy()
3725 tr_req[1].dicnt1 = 1; in udma_prep_dma_memcpy()
3726 tr_req[1].dicnt2 = 1; in udma_prep_dma_memcpy()
3727 tr_req[1].dicnt3 = 1; in udma_prep_dma_memcpy()
3730 cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, in udma_prep_dma_memcpy()
5040 struct cppi5_tr_type1_t *tr_req; in udma_setup_rx_flush() local
5087 tr_req = hwdesc->tr_req_base; in udma_setup_rx_flush()
5088 cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false, in udma_setup_rx_flush()
5090 cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT); in udma_setup_rx_flush()
5092 tr_req->addr = rx_flush->buffer_paddr; in udma_setup_rx_flush()
5093 tr_req->icnt0 = rx_flush->buffer_size; in udma_setup_rx_flush()
5094 tr_req->icnt1 = 1; in udma_setup_rx_flush()