36 #define AE(handle, ae) ((handle)->hal_handle->aes[ae])
380 	unsigned long ae_mask = handle->hal_handle->ae_mask;  in qat_hal_check_ae_alive()
385 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_check_ae_alive()
419 	unsigned long ae_mask = handle->hal_handle->ae_mask;  in qat_hal_reset_timestamp()
430 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_reset_timestamp()
478 	unsigned long ae_mask = handle->hal_handle->ae_mask;  in qat_hal_clr_reset()
501 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_clr_reset()
506 				    handle->hal_handle->upc_mask &  in qat_hal_clr_reset()
607 	unsigned long ae_mask = handle->hal_handle->ae_mask;  in qat_hal_clear_xfer()
611 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_clear_xfer()
623 	unsigned long ae_mask = handle->hal_handle->ae_mask;  in qat_hal_clear_gpr()
631 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_clear_gpr()
644 				    handle->hal_handle->upc_mask &  in qat_hal_clear_gpr()
654 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_clear_gpr()
670 				    handle->hal_handle->upc_mask &  in qat_hal_clear_gpr()
790 	handle->hal_handle->revision_id = accel_dev->accel_pci_dev.revid;  in qat_hal_chip_init()
791 	handle->hal_handle->ae_mask = hw_data->ae_mask;  in qat_hal_chip_init()
792 	handle->hal_handle->admin_ae_mask = hw_data->admin_ae_mask;  in qat_hal_chip_init()
793 	handle->hal_handle->slice_mask = hw_data->accel_mask;  in qat_hal_chip_init()
796 	handle->hal_handle->upc_mask = 0x1ffff;  in qat_hal_chip_init()
797 	handle->hal_handle->max_ustore = 0x4000;  in qat_hal_chip_init()
799 	ae_mask = handle->hal_handle->ae_mask;  in qat_hal_chip_init()
801 		handle->hal_handle->aes[ae].free_addr = 0;  in qat_hal_chip_init()
802 		handle->hal_handle->aes[ae].free_size =  in qat_hal_chip_init()
803 		    handle->hal_handle->max_ustore;  in qat_hal_chip_init()
804 		handle->hal_handle->aes[ae].ustore_size =  in qat_hal_chip_init()
805 		    handle->hal_handle->max_ustore;  in qat_hal_chip_init()
806 		handle->hal_handle->aes[ae].live_ctx_mask =  in qat_hal_chip_init()
810 	handle->hal_handle->ae_max_num = max_en_ae_id + 1;  in qat_hal_chip_init()
813 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_chip_init()
831 	handle->hal_handle = kzalloc(sizeof(*handle->hal_handle), GFP_KERNEL);  in qat_hal_init()
832 	if (!handle->hal_handle) {  in qat_hal_init()
869 	kfree(handle->hal_handle);  in qat_hal_init()
880 	kfree(handle->hal_handle);  in qat_hal_deinit()
886 	unsigned long ae_mask = handle->hal_handle->ae_mask;  in qat_hal_start()
908 		for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_start()
928 			    handle->hal_handle->upc_mask & upc);  in qat_hal_set_pc()
1000 	if ((inst_num > handle->hal_handle->max_ustore) || !micro_inst) {  in qat_hal_exec_micro_inst()
1029 	savpc = (savpc & handle->hal_handle->upc_mask) >> 0;  in qat_hal_exec_micro_inst()
1059 		*endpc = ctx_status & handle->hal_handle->upc_mask;  in qat_hal_exec_micro_inst()
1067 			    handle->hal_handle->upc_mask & savpc);  in qat_hal_exec_micro_inst()
1294 	if ((unsigned int)alloc_inst_size > handle->hal_handle->max_ustore)  in qat_hal_batch_wr_lm()
1295 		alloc_inst_size = handle->hal_handle->max_ustore;  in qat_hal_batch_wr_lm()