Lines Matching refs:NPCM7XX_REG_TCSR0
22 #define NPCM7XX_REG_TCSR0 0x0 /* Timer 0 Control and Status Register */ macro
61 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_resume()
63 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_resume()
73 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_shutdown()
75 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_shutdown()
85 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_oneshot()
88 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_oneshot()
100 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_periodic()
103 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_timer_periodic()
115 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_clockevent_set_next_event()
117 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); in npcm7xx_clockevent_set_next_event()
158 timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR0); in npcm7xx_clockevents_init()