Lines Matching defs:socfpga_gate_clk

43 struct socfpga_gate_clk {  struct
44 	struct clk_gate hw;
45 	char *parent_name;
46 	u32 fixed_div;
47 	void __iomem *div_reg;
48 	void __iomem *bypass_reg;
49 	struct regmap *sys_mgr_base_addr;
50 	u32 width;	/* only valid if div_reg != 0 */
51 	u32 shift;	/* only valid if div_reg != 0 */
52 	u32 bypass_shift;      /* only valid if bypass_reg != 0 */
53 	u32 clk_phase[2];