Lines Matching refs:PCLKCON
31 #define PCLKCON 0x34 macro
58 PCLKCON,
130 GATE(PCLK_GPIO, "gpio", "pclk", PCLKCON, 13, CLK_IGNORE_UNUSED, 0),
131 GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0),
132 GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0),
133 GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0),
134 GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0),
135 GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0),
136 GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0),
137 GATE(PCLK_SPI0, "spi0", "pclk", PCLKCON, 6, 0, 0),
138 GATE(PCLK_I2C0, "i2c0", "pclk", PCLKCON, 4, 0, 0),
139 GATE(PCLK_UART3, "uart3", "pclk", PCLKCON, 3, 0, 0),
140 GATE(PCLK_UART2, "uart2", "pclk", PCLKCON, 2, 0, 0),
141 GATE(PCLK_UART1, "uart1", "pclk", PCLKCON, 1, 0, 0),
142 GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0),
219 GATE(PCLK_PCM, "pcm", "pclk", PCLKCON, 19, 0, 0),
260 GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 15, 0, 0),
261 GATE(PCLK_SDI, "sdi", "pclk", PCLKCON, 5, 0, 0),
299 GATE(PCLK_I2S1, "i2s1", "pclk", PCLKCON, 17, 0, 0),
300 GATE(PCLK_I2C1, "i2c1", "pclk", PCLKCON, 16, 0, 0),
301 GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 14, 0, 0),