Lines Matching refs:GATE
517 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0,
519 GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0,
521 GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED,
523 GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0,
536 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0,
539 GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0,
541 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
543 GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0,
545 GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED,
562 GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0,
564 GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0,
566 GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0,
569 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0,
571 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
573 GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0,
575 GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED,
588 GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
598 GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0,
603 GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED,
605 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED,
607 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0,
609 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0,
611 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0,
613 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0,
623 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
636 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
649 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0,
662 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0,
675 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0,
688 GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0,
701 GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0,
707 GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0,
712 GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0,
714 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0,
725 GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0,
735 GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0,
740 GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0,
742 GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0,
752 GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0,
754 GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0,
762 GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0,
764 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
766 GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
768 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0,
770 GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0,
772 GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0,
774 GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0,
779 GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0,
781 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0,
786 GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0,
788 GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0,
796 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
808 GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0,
810 GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0,
812 GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0,
814 GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0,
816 GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
818 GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
820 GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
822 GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0,
824 GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0,
826 GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
828 GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
830 GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
832 GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0,
834 GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0,
836 GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
838 GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
840 GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,
842 GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0,
844 GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0,
846 GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0,
848 GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0,
850 GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0,
852 GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0,
854 GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0,
856 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0,
858 GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
863 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0,
865 GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
873 GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0,
886 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0,
894 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0,
902 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 0,
904 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 0,
912 GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0,
940 GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0,
942 GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0,
944 GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0,
946 GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0,
948 GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0,
956 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0,
958 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0,
966 GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0,
1002 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0,
1004 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0,
1009 GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0,
1011 GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0,
1013 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0,
1018 GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0,
1043 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0,
1045 GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
1056 GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0,
1058 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0,
1060 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0,
1062 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0,
1064 GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0,
1066 GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1068 GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0,
1070 GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0,
1072 GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0,
1074 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0,
1087 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
1089 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0,
1102 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
1104 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
1109 GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0,
1111 GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0,
1116 GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS),
1120 GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0,
1122 GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0,
1124 GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0,
1126 GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0,
1128 GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0,
1130 GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0,
1140 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
1142 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
1153 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
1155 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
1174 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0,
1182 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0,
1184 GATE(CLK_SARADC, "clk_saradc", "xin24m", 0,
1186 GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED,
1188 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0,
1190 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
1192 GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED,
1194 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED,
1196 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0,
1199 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0,
1208 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
1211 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0,
1220 GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
1223 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0,
1232 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
1235 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0,
1244 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
1247 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0,
1256 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
1259 GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0,
1268 GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0,
1271 GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0,
1280 GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0,
1283 GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0,
1292 GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0,
1295 GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0,
1304 GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0,
1307 GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0,
1312 GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0,
1317 GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0,
1325 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0,
1327 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
1329 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0,
1331 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0,
1333 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0,
1335 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0,
1337 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0,
1339 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0,
1341 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0,
1343 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0,
1345 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0,
1350 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0,
1355 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0,
1360 GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0,
1364 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS),
1368 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
1370 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0,
1375 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
1377 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0,
1382 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
1387 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0,
1389 GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0,
1391 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0,
1393 GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0,
1395 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0,
1397 GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0,
1399 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0,
1401 GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0,
1403 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0,
1405 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
1407 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
1409 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
1411 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
1413 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
1415 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
1431 GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0,
1436 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0,
1438 GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0,
1440 GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0,
1442 GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0,
1444 GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0,
1446 GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0,
1448 GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0,
1450 GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0,
1452 GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0,
1454 GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0,
1469 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0,
1471 GATE(CLK_PMU, "clk_pmu", "xin24m", 0,
1473 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
1478 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0,
1497 GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
1500 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
1505 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
1510 GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0,
1512 GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
1514 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
1516 GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
1521 GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0,
1525 GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0,
1529 GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0,
1533 GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0,
1540 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
1547 GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0,
1554 GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0,
1561 GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0,
1565 GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0,
1567 GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0,
1569 GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0,