Lines Matching refs:apbc_base
76 void __iomem *apbc_base; in pxa168_clk_init() local
90 apbc_base = ioremap(apbc_phys, SZ_4K); in pxa168_clk_init()
91 if (!apbc_base) { in pxa168_clk_init()
165 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); in pxa168_clk_init()
169 apbc_base + APBC_TWSI1, 10, 0, &clk_lock); in pxa168_clk_init()
173 apbc_base + APBC_GPIO, 10, 0, &clk_lock); in pxa168_clk_init()
177 apbc_base + APBC_KPC, 10, 0, &clk_lock); in pxa168_clk_init()
181 apbc_base + APBC_RTC, 10, 0, &clk_lock); in pxa168_clk_init()
185 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in pxa168_clk_init()
189 apbc_base + APBC_PWM1, 10, 0, &clk_lock); in pxa168_clk_init()
193 apbc_base + APBC_PWM2, 10, 0, &clk_lock); in pxa168_clk_init()
197 apbc_base + APBC_PWM3, 10, 0, &clk_lock); in pxa168_clk_init()
203 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); in pxa168_clk_init()
208 apbc_base + APBC_UART0, 10, 0, &clk_lock); in pxa168_clk_init()
214 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); in pxa168_clk_init()
219 apbc_base + APBC_UART1, 10, 0, &clk_lock); in pxa168_clk_init()
225 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); in pxa168_clk_init()
230 apbc_base + APBC_UART2, 10, 0, &clk_lock); in pxa168_clk_init()
236 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); in pxa168_clk_init()
239 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, in pxa168_clk_init()
246 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); in pxa168_clk_init()
249 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, in pxa168_clk_init()
256 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); in pxa168_clk_init()
259 clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2, in pxa168_clk_init()
266 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); in pxa168_clk_init()
269 clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3, in pxa168_clk_init()
276 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock); in pxa168_clk_init()
279 clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4, in pxa168_clk_init()