Lines Matching refs:to_clk

98 	to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
102 	to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
106 	to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
109 	to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
112 	to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
115 	to_clk(imx_clk_hw_fixed(name, rate))
118 	to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
121 	to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
124 	to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
127 	to_clk(imx_clk_hw_gate(name, parent, reg, shift))
130 	to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
133 	to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
136 	to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
139 	to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
142 	to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
145 	to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
148 	to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
151 	to_clk(imx_clk_hw_pllv1(type, name, parent, base))
154 	to_clk(imx_clk_hw_pllv2(name, parent, base))
157 	to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
331 static inline struct clk *to_clk(struct clk_hw *hw)  in to_clk()  function