20 #define GNRL_CTL	0x0  macro
280 	return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, 0,  in clk_pll14xx_wait_lock()
310 	tmp = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
312 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
316 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
320 	writel(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
336 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
345 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
375 	gnrl_ctl = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
377 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
381 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
400 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
409 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
424 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
428 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
430 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
437 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
447 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_is_prepared()
461 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_unprepare()
463 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_unprepare()
529 	val = readl_relaxed(pll->base + GNRL_CTL);  in imx_dev_clk_hw_pll14xx()
531 	writel_relaxed(val, pll->base + GNRL_CTL);  in imx_dev_clk_hw_pll14xx()