283 	void __iomem *pll_base;  in mx50_clocks_init()  local
286 	pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);  in mx50_clocks_init()
287 	WARN_ON(!pll_base);  in mx50_clocks_init()
288 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);  in mx50_clocks_init()
290 	pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);  in mx50_clocks_init()
291 	WARN_ON(!pll_base);  in mx50_clocks_init()
292 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);  in mx50_clocks_init()
294 	pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);  in mx50_clocks_init()
295 	WARN_ON(!pll_base);  in mx50_clocks_init()
296 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);  in mx50_clocks_init()
368 	void __iomem *pll_base;  in mx51_clocks_init()  local
371 	pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);  in mx51_clocks_init()
372 	WARN_ON(!pll_base);  in mx51_clocks_init()
373 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);  in mx51_clocks_init()
375 	pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);  in mx51_clocks_init()
376 	WARN_ON(!pll_base);  in mx51_clocks_init()
377 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);  in mx51_clocks_init()
379 	pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);  in mx51_clocks_init()
380 	WARN_ON(!pll_base);  in mx51_clocks_init()
381 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);  in mx51_clocks_init()
474 	void __iomem *pll_base;  in mx53_clocks_init()  local
477 	pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);  in mx53_clocks_init()
478 	WARN_ON(!pll_base);  in mx53_clocks_init()
479 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);  in mx53_clocks_init()
481 	pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);  in mx53_clocks_init()
482 	WARN_ON(!pll_base);  in mx53_clocks_init()
483 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);  in mx53_clocks_init()
485 	pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);  in mx53_clocks_init()
486 	WARN_ON(!pll_base);  in mx53_clocks_init()
487 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);  in mx53_clocks_init()
489 	pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);  in mx53_clocks_init()
490 	WARN_ON(!pll_base);  in mx53_clocks_init()
491 	clk[IMX5_CLK_PLL4_SW]		= imx_clk_pllv2("pll4_sw", "osc", pll_base);  in mx53_clocks_init()