Lines Matching refs:LPSC
34 LPSC(0, 0, arm, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
36 LPSC(1, 0, dsp, pll1_sysclk1, NULL, LPSC_ALWAYS_ENABLED),
37 LPSC(4, 0, edma_cc, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
38 LPSC(5, 0, edma_tc0, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
39 LPSC(6, 0, edma_tc1, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
40 LPSC(7, 0, edma_tc2, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
41 LPSC(8, 0, edma_tc3, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
42 LPSC(10, 0, ide, pll1_sysclk4, ide_clkdev, 0),
43 LPSC(14, 0, emac, pll1_sysclk3, emac_clkdev, 0),
44 LPSC(16, 0, vpif0, ref_clk, NULL, LPSC_ALWAYS_ENABLED),
45 LPSC(17, 0, vpif1, ref_clk, NULL, LPSC_ALWAYS_ENABLED),
46 LPSC(21, 0, aemif, pll1_sysclk3, aemif_clkdev, LPSC_ALWAYS_ENABLED),
47 LPSC(22, 0, mcasp0, pll1_sysclk3, mcasp0_clkdev, 0),
48 LPSC(23, 0, mcasp1, pll1_sysclk3, mcasp1_clkdev, 0),
49 LPSC(26, 0, uart0, aux_clkin, uart0_clkdev, 0),
50 LPSC(27, 0, uart1, aux_clkin, uart1_clkdev, 0),
51 LPSC(28, 0, uart2, aux_clkin, uart2_clkdev, 0),
53 LPSC(29, 0, pwm0, pll1_sysclk3, NULL, LPSC_ALWAYS_ENABLED),
55 LPSC(30, 0, pwm1, pll1_sysclk3, NULL, LPSC_ALWAYS_ENABLED),
56 LPSC(31, 0, i2c, pll1_sysclk3, i2c_clkdev, 0),
57 LPSC(33, 0, gpio, pll1_sysclk3, gpio_clkdev, 0),
58 LPSC(34, 0, timer0, pll1_sysclk3, timer0_clkdev, LPSC_ALWAYS_ENABLED),
59 LPSC(35, 0, timer1, pll1_sysclk3, NULL, 0),