Lines Matching refs:OWL_DIVIDER_HW
209 OWL_DIVIDER_HW(CMU_BUSCLK1, 16, 2, 0, NULL),
215 OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
237 OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table),
243 OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table),
249 OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table),
273 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
279 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
285 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
291 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
297 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
303 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
334 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
340 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
346 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
352 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
358 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
364 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
370 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
376 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
382 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
388 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, i2s_div_table),
394 OWL_DIVIDER_HW(CMU_AUDIOPLL, 28, 4, 0, i2s_div_table),
400 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, nand_div_table),
406 OWL_DIVIDER_HW(CMU_NANDCCLK, 4, 3, 0, nand_div_table),