32 #define PCIC_WRITE(x,v) writel((v), PCI_REG(x))  macro
62 	PCIC_WRITE(SH7751_PCIBCR1, bcr1);	 /* PCIC BCR1 */  in pci_fixup_pcic()
63 	PCIC_WRITE(SH7751_PCIBCR2, bcr2);     /* PCIC BCR2 */  in pci_fixup_pcic()
64 	PCIC_WRITE(SH7751_PCIWCR1, wcr1);     /* PCIC WCR1 */  in pci_fixup_pcic()
65 	PCIC_WRITE(SH7751_PCIWCR2, wcr2);     /* PCIC WCR2 */  in pci_fixup_pcic()
66 	PCIC_WRITE(SH7751_PCIWCR3, wcr3);     /* PCIC WCR3 */  in pci_fixup_pcic()
68 	PCIC_WRITE(SH7751_PCIMCR, mcr);      /* PCIC MCR */  in pci_fixup_pcic()
72 	PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);  in pci_fixup_pcic()
73 	PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);  in pci_fixup_pcic()
76 	PCIC_WRITE(SH7751_PCICONF1,	0xF39000C7); /* Bus Master, Mem & I/O access */  in pci_fixup_pcic()
77 	PCIC_WRITE(SH7751_PCICONF2,	0x00000000); /* PCI Class code & Revision ID */  in pci_fixup_pcic()
78 	PCIC_WRITE(SH7751_PCICONF4,	0xab000001); /* PCI I/O address (local regs) */  in pci_fixup_pcic()
79 	PCIC_WRITE(SH7751_PCICONF5,	0x0c000000); /* PCI MEM address (local RAM)  */  in pci_fixup_pcic()
80 	PCIC_WRITE(SH7751_PCICONF6,	0xd0000000); /* PCI MEM address (unused)     */  in pci_fixup_pcic()
81 	PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */  in pci_fixup_pcic()
82 	PCIC_WRITE(SH7751_PCILSR0, 0x03f00000);   /* MEM (full 64M exposed)       */  in pci_fixup_pcic()
83 	PCIC_WRITE(SH7751_PCILSR1, 0x00000000);   /* MEM (unused)                 */  in pci_fixup_pcic()
84 	PCIC_WRITE(SH7751_PCILAR0, 0x0c000000);   /* MEM (direct map from PCI)    */  in pci_fixup_pcic()
85 	PCIC_WRITE(SH7751_PCILAR1, 0x00000000);   /* MEM (unused)                 */  in pci_fixup_pcic()
88 	PCIC_WRITE(SH7751_PCICR, 0xa5000001);  in pci_fixup_pcic()
104 	PCIC_WRITE(SH7751_PCIMBR, chan->resources[1].start);  in pci_fixup_pcic()
107 	PCIC_WRITE(SH7751_PCIIOBR, (chan->resources[0].start & SH7751_PCIIOBR_MASK));  in pci_fixup_pcic()