Lines Matching refs:B_16

79 	B_16,	/* Base register starting at position 16 */  enumerator
141 	[B_16]	 = {  4, 16, OPERAND_BASE | OPERAND_GPR },
214 	[INSTR_RIS_RURDI]    = { R_8, I8_32, U4_12, D_20, B_16, 0 },
215 	[INSTR_RIS_RURDU]    = { R_8, U8_32, U4_12, D_20, B_16, 0 },
249 	[INSTR_RRS_RRRDU]    = { R_8, R_12, U4_32, D_20, B_16 },
256 	[INSTR_RSL_LRDFU]    = { F_32, D_20, L8_8, B_16, U4_36, 0 },
257 	[INSTR_RSL_R0RD]     = { D_20, L4_8, B_16, 0, 0, 0 },
258 	[INSTR_RSY_AARD]     = { A_8, A_12, D20_20, B_16, 0, 0 },
259 	[INSTR_RSY_CCRD]     = { C_8, C_12, D20_20, B_16, 0, 0 },
260 	[INSTR_RSY_RDRU]     = { R_8, D20_20, B_16, U4_12, 0, 0 },
261 	[INSTR_RSY_RRRD]     = { R_8, R_12, D20_20, B_16, 0, 0 },
262 	[INSTR_RSY_RURD]     = { R_8, U4_12, D20_20, B_16, 0, 0 },
263 	[INSTR_RSY_RURD2]    = { R_8, D20_20, B_16, U4_12, 0, 0 },
264 	[INSTR_RS_AARD]	     = { A_8, A_12, D_20, B_16, 0, 0 },
265 	[INSTR_RS_CCRD]	     = { C_8, C_12, D_20, B_16, 0, 0 },
266 	[INSTR_RS_R0RD]	     = { R_8, D_20, B_16, 0, 0, 0 },
267 	[INSTR_RS_RRRD]	     = { R_8, R_12, D_20, B_16, 0, 0 },
268 	[INSTR_RS_RURD]	     = { R_8, U4_12, D_20, B_16, 0, 0 },
269 	[INSTR_RXE_FRRD]     = { F_8, D_20, X_12, B_16, 0, 0 },
270 	[INSTR_RXE_RRRDU]    = { R_8, D_20, X_12, B_16, U4_32, 0 },
271 	[INSTR_RXF_FRRDF]    = { F_32, F_8, D_20, X_12, B_16, 0 },
272 	[INSTR_RXY_FRRD]     = { F_8, D20_20, X_12, B_16, 0, 0 },
273 	[INSTR_RXY_RRRD]     = { R_8, D20_20, X_12, B_16, 0, 0 },
274 	[INSTR_RXY_URRD]     = { U4_8, D20_20, X_12, B_16, 0, 0 },
275 	[INSTR_RX_FRRD]	     = { F_8, D_20, X_12, B_16, 0, 0 },
276 	[INSTR_RX_RRRD]	     = { R_8, D_20, X_12, B_16, 0, 0 },
277 	[INSTR_RX_URRD]	     = { U4_8, D_20, X_12, B_16, 0, 0 },
278 	[INSTR_SIL_RDI]	     = { D_20, B_16, I16_32, 0, 0, 0 },
279 	[INSTR_SIL_RDU]	     = { D_20, B_16, U16_32, 0, 0, 0 },
280 	[INSTR_SIY_IRD]	     = { D20_20, B_16, I8_8, 0, 0, 0 },
281 	[INSTR_SIY_RD]	     = { D20_20, B_16, 0, 0, 0, 0 },
282 	[INSTR_SIY_URD]	     = { D20_20, B_16, U8_8, 0, 0, 0 },
283 	[INSTR_SI_RD]	     = { D_20, B_16, 0, 0, 0, 0 },
284 	[INSTR_SI_URD]	     = { D_20, B_16, U8_8, 0, 0, 0 },
285 	[INSTR_SMI_U0RDP]    = { U4_8, J16_32, D_20, B_16, 0, 0 },
286 	[INSTR_SSE_RDRD]     = { D_20, B_16, D_36, B_32, 0, 0 },
287 	[INSTR_SSF_RRDRD]    = { D_20, B_16, D_36, B_32, R_8, 0 },
288 	[INSTR_SSF_RRDRD2]   = { R_8, D_20, B_16, D_36, B_32, 0 },
289 	[INSTR_SS_L0RDRD]    = { D_20, L8_8, B_16, D_36, B_32, 0 },
290 	[INSTR_SS_L2RDRD]    = { D_20, B_16, D_36, L8_8, B_32, 0 },
291 	[INSTR_SS_LIRDRD]    = { D_20, L4_8, B_16, D_36, B_32, U4_12 },
292 	[INSTR_SS_LLRDRD]    = { D_20, L4_8, B_16, D_36, L4_12, B_32 },
293 	[INSTR_SS_RRRDRD]    = { D_20, R_8, B_16, D_36, B_32, R_12 },
294 	[INSTR_SS_RRRDRD2]   = { R_8, D_20, B_16, R_12, D_36, B_32 },
295 	[INSTR_SS_RRRDRD3]   = { R_8, R_12, D_20, B_16, D_36, B_32 },
297 	[INSTR_S_RD]	     = { D_20, B_16, 0, 0, 0, 0 },
329 	[INSTR_VRS_RRDV]     = { V_32, R_12, D_20, B_16, 0, 0 },
330 	[INSTR_VRS_RVRDU]    = { R_8, V_12, D_20, B_16, U4_32, 0 },
331 	[INSTR_VRS_VRRD]     = { V_8, R_12, D_20, B_16, 0, 0 },
332 	[INSTR_VRS_VRRDU]    = { V_8, R_12, D_20, B_16, U4_32, 0 },
333 	[INSTR_VRS_VVRDU]    = { V_8, V_12, D_20, B_16, U4_32, 0 },
334 	[INSTR_VRV_VVXRDU]   = { V_8, D_20, VX_12, B_16, U4_32, 0 },
335 	[INSTR_VRX_VRRDU]    = { V_8, D_20, X_12, B_16, U4_32, 0 },
337 	[INSTR_VSI_URDV]     = { V_32, D_20, B_16, U8_8, 0, 0 },