Lines Matching refs:cvmx_read_csr
254 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); in dwc3_octeon_config_power()
259 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); in dwc3_octeon_config_power()
264 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio)); in dwc3_octeon_config_power()
271 uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); in dwc3_octeon_config_power()
277 uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); in dwc3_octeon_config_power()
359 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
366 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
377 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
381 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
388 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
393 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
433 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
447 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
455 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
460 uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); in dwc3_octeon_clocks_start()
472 shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG); in dwc3_octeon_set_endian_mode()
491 uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index)); in dwc3_octeon_phy_reset()