Lines Matching refs:type
44 unsigned int type; member
138 static int s3c_irq_type(struct irq_data *data, unsigned int type) in s3c_irq_type() argument
140 switch (type) { in s3c_irq_type()
153 pr_err("No such irq type %d\n", type); in s3c_irq_type()
164 unsigned int type) in s3c_irqext_type_set() argument
174 switch (type) in s3c_irqext_type_set()
201 pr_err("No such irq type %d\n", type); in s3c_irqext_type_set()
212 static int s3c_irqext_type(struct irq_data *data, unsigned int type) in s3c_irqext_type() argument
238 extint_offset, type); in s3c_irqext_type()
241 static int s3c_irqext0_type(struct irq_data *data, unsigned int type) in s3c_irqext0_type() argument
257 extint_offset, type); in s3c_irqext0_type()
445 switch (irq_data->type) { in s3c24xx_irq_map()
476 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type); in s3c24xx_irq_map()
482 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) { in s3c24xx_irq_map()
622 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
623 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
624 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
625 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
626 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
627 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
628 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
629 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
630 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
631 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
632 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
633 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
634 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
635 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
636 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
637 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
638 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
639 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
640 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
641 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
642 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
643 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
644 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
645 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
650 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
651 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
652 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
653 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
654 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
655 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
656 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
657 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
658 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
659 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
660 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
661 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
662 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
663 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
664 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
665 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
666 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
667 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
668 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
669 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
670 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
671 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
672 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
673 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
674 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
675 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
676 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
677 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
678 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
679 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
680 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
681 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
685 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
686 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
687 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
688 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
689 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
690 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
691 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
692 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
693 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
694 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
695 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
719 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
720 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
721 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
722 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
723 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
724 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
725 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
726 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
727 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
728 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
729 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
730 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
731 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
732 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
733 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
734 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
735 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
736 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
737 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
738 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
739 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
740 { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
741 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
742 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
743 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
744 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
745 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
746 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
747 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
748 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
749 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
750 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
754 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
755 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
756 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
757 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
758 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
759 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
760 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
761 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
762 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
763 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
764 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
765 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
766 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
767 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
768 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
769 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
770 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
771 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
772 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
773 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
774 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
775 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
776 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
777 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
781 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
782 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
783 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
784 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
785 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
786 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
787 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
788 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
789 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
790 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
791 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
792 { .type = S3C_IRQTYPE_NONE, },
793 { .type = S3C_IRQTYPE_NONE, },
794 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
795 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
821 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
822 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
823 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
824 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
825 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
826 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
827 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
828 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
829 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
830 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
831 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
832 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
833 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
834 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
835 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
836 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
837 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
838 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
839 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
840 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
841 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
842 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
843 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
844 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
845 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
846 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
847 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
848 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
849 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
850 { .type = S3C_IRQTYPE_NONE, },
851 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
852 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
856 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
857 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
858 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
859 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
860 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
861 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
862 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
863 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
864 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
865 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
866 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
867 { .type = S3C_IRQTYPE_NONE }, /* reserved */
868 { .type = S3C_IRQTYPE_NONE }, /* reserved */
869 { .type = S3C_IRQTYPE_NONE }, /* reserved */
870 { .type = S3C_IRQTYPE_NONE }, /* reserved */
871 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
872 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
873 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
874 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
875 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
876 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
877 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
878 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
879 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
880 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
881 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
882 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
883 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
884 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
888 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
889 { .type = S3C_IRQTYPE_NONE }, /* reserved */
890 { .type = S3C_IRQTYPE_NONE }, /* reserved */
891 { .type = S3C_IRQTYPE_NONE }, /* reserved */
892 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
893 { .type = S3C_IRQTYPE_NONE }, /* reserved */
894 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
924 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
925 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
926 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
927 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
928 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
929 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
930 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
931 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
932 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
933 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
934 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
935 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
936 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
937 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
938 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
939 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
940 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
941 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
942 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
943 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
944 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
945 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
946 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
947 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
948 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
949 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
950 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
951 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
952 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
953 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
954 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
955 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
959 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
960 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
961 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
962 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
963 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
964 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
965 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
966 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
967 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
968 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
969 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
970 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
971 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
972 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
973 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
999 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1000 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1001 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1002 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1003 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1004 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1005 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1006 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1007 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1008 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
1009 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1010 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1011 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1012 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1013 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1014 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1015 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
1016 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
1017 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
1018 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
1019 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
1020 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
1021 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1022 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1023 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
1024 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1025 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1026 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1027 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1028 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1029 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1030 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1034 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1035 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1036 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1037 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1038 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1039 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1040 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1041 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1042 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1043 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1044 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1045 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1046 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1072 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1073 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1074 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1075 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1076 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1077 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1078 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1079 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1080 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1081 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
1082 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1083 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1084 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1085 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1086 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1087 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1088 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
1089 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
1090 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
1091 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
1092 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
1093 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
1094 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1095 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1096 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
1097 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1098 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1099 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1100 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1101 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1102 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1103 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1108 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1109 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1110 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1111 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1112 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1113 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1114 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1115 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1116 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1117 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1118 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1119 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1120 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1121 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1122 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1123 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1124 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1125 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1126 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1127 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1128 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1129 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1130 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1131 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1132 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1133 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1134 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1135 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1136 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */