Lines Matching refs:_PMREG
121 #define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\ macro
123 #define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000)
124 #define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014)
125 #define LPC32XX_CLKPWR_P01_ER _PMREG(0x018)
126 #define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C)
127 #define LPC32XX_CLKPWR_INT_ER _PMREG(0x020)
128 #define LPC32XX_CLKPWR_INT_RS _PMREG(0x024)
129 #define LPC32XX_CLKPWR_INT_SR _PMREG(0x028)
130 #define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C)
131 #define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030)
132 #define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034)
133 #define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038)
134 #define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C)
135 #define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040)
136 #define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044)
137 #define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048)
138 #define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C)
139 #define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050)
140 #define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054)
141 #define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058)
142 #define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060)
143 #define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064)
144 #define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068)
145 #define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C)
146 #define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070)
147 #define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074)
148 #define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078)
149 #define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C)
150 #define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080)
151 #define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090)
152 #define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4)
153 #define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8)
154 #define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC)
155 #define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0)
156 #define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4)
157 #define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8)
158 #define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC)
159 #define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0)
160 #define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4)
161 #define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8)
162 #define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0)
163 #define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4)
164 #define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8)
165 #define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC)
166 #define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0)
167 #define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4)
168 #define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8)
169 #define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC)
170 #define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x))