Lines Matching refs:architectures

31 memory, but as accesses to a device. Some architectures define devices
44 space to the kernel. Most architectures allocate new address space each
153 ``void __iomem *reg``. On most architectures it is a regular pointer that
160 While on most architectures, ioremap() creates a page table entry for an
162 architectures require special instructions for MMIO, and the ``__iomem`` pointer
182   On architectures that require an expensive barrier for serializing against
197   for mapping PCI I/O space with pci_iomap() or ioport_map(). On architectures
200   other architectures, these are simply aliases.
211   Note: On some architectures, the normal readl()/writel() functions
223   on 32-bit architectures but allow two consecutive 32-bit accesses instead.
229   readq()/writeq() to them on architectures that do not provide 64-bit access
249   architectures, these are mapped to readl()/writel() style accessors
254   still be in progress. On architectures that correctly implement this, I/O port
256   implementations and CPU architectures however fail to implement non-posted I/O
259   In some architectures, the I/O port number space has a 1:1 mapping to
272   accessors add a small delay. On architectures that do not have ISA buses,
290 Some architectures support multiple modes for mapping device memory.
311   respect to each other. On some architectures, this relies on barriers in
374 architectures and buses, ioremap() mappings have posted write semantics, which
390 The bare ioremap_np() is only available on some architectures; on others, it
399 always posted, even on architectures that otherwise implement ioremap_np().