Lines Matching refs:idle
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
21 representing the range of dynamic idle states that a processor can enter at
23 parameters required to enter/exit specific idle states on a given processor.
26 2 - ARM idle states
40 PM implementation to put the processor in different idle states (which include
41 states listed above; "off" state is not an idle state since it does not have
48 The device tree binding definition for ARM idle states is the subject of this
52 3 - RISC-V idle states
56 suspend (or idle) states (ranging from simple WFI, power gating, etc). The
60 The platform specific suspend (or idle) states of a hart can be either
67 4 - idle-states definitions
72 triggered upon idle states entry and exit.
75 properties required to enter and exit an idle state:
87 Diagram 1: CPU idle state execution phases
91 PREP: Preparation phase before committing the hardware to idle mode
98 ENTRY: The hardware is committed to idle mode. This period must run
101 IDLE: This is the actual energy-saving idle period. This may last
107 entry-latency: Worst case latency required to enter the idle state. The
111 idle state to be worthwhile energywise.
119 An idle CPU requires the expected min-residency time to select the most
120 appropriate idle state based on the expected expiry time of the next IRQ
125 of an idle state, e.g.:
140 idle state, and possibly to prevent that to guarantee reliable device
173 and denotes the energy costs incurred while entering and leaving the idle
176 shallower slope and essentially represents the energy consumption of the idle
179 min-residency is defined for a given idle state as the minimum expected
185 For sake of simplicity, let's consider a system with two idle states IDLE1,
211 Graph 2: idle states min-residency example
213 In graph 2 above, that takes into account idle states entry/exit energy
214 costs, it is clear that if the idle state residency time (i.e. time till next
215 wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
222 idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
226 shallower states in a system with multiple idle states) is defined
230 The definitions provided in this section underpin the idle states
234 5 - idle-states node
237 The processor idle states are defined within the idle-states node, which is
239 processor idle states, defined as device tree nodes, are listed.
241 On ARM systems, it is a container of processor idle states nodes. If the
243 just supports idle_standby, an idle-states node is not required.
272 const: idle-states
282 node[5] that is responsible for setting up CPU idle management in the OS
290 Each state node represents an idle state description and must be defined
293 The idle state entered by executing the wfi instruction (idle_standby
299 idle-states node. Please refer to the entry-method bindings
305 - arm,idle-state
306 - riscv,idle-state
314 (i.e. idle states node with entry-method property is set to "psci")
322 This property is required in idle state nodes of device tree meant
334 Worst case latency in microseconds required to enter the idle state.
338 Worst case latency in microseconds required to exit the idle state.
345 and entry, for this idle state to be considered worthwhile energy wise
361 idle-state-name:
364 A string used as a descriptive name for the idle state.
388 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
397 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
406 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
415 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
424 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
433 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
442 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
451 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
460 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
469 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
478 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
487 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
496 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
505 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
514 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
523 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
527 idle-states {
531 compatible = "arm,idle-state";
539 compatible = "arm,idle-state";
549 compatible = "arm,idle-state";
558 compatible = "arm,idle-state";
568 compatible = "arm,idle-state";
576 compatible = "arm,idle-state";
586 compatible = "arm,idle-state";
596 compatible = "arm,idle-state";
618 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
625 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
632 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
639 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
646 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
653 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
660 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
667 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
670 idle-states {
672 compatible = "arm,idle-state";
681 compatible = "arm,idle-state";
690 compatible = "arm,idle-state";
699 compatible = "arm,idle-state";
722 cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
738 cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
754 cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
770 cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
780 idle-states {
782 compatible = "riscv,idle-state";
790 compatible = "riscv,idle-state";
798 compatible = "riscv,idle-state";
808 compatible = "riscv,idle-state";
818 compatible = "riscv,idle-state";
826 compatible = "riscv,idle-state";
834 compatible = "riscv,idle-state";
844 compatible = "riscv,idle-state";