313 	OUTREG(MPP_TB_CONFIG, temp);  in radeon_map_ROM()
856 	OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length +  in radeonfb_pan_display()
896 			OUTREG(LVDS_GEN_CNTL, tmp);  in radeonfb_ioctl()
910 			OUTREG(CRTC_EXT_CNTL, tmp);  in radeonfb_ioctl()
966 	OUTREG(CRTC_EXT_CNTL, val);  in radeon_screen_blank()
988 				OUTREG(LVDS_GEN_CNTL, target_val);  in radeon_screen_blank()
990 				OUTREG(LVDS_GEN_CNTL, target_val  in radeon_screen_blank()
997 					OUTREG(LVDS_GEN_CNTL, target_val);  in radeon_screen_blank()
1008 			OUTREG(LVDS_GEN_CNTL, val);  in radeon_screen_blank()
1021 			OUTREG(LVDS_GEN_CNTL, val);  in radeon_screen_blank()
1024 			OUTREG(LVDS_GEN_CNTL, val);  in radeon_screen_blank()
1091 		                OUTREG(PALETTE_INDEX, pindex>>1);  in radeon_setcolreg()
1092 	       	         	OUTREG(PALETTE_DATA,  in radeon_setcolreg()
1101 			OUTREG(PALETTE_INDEX, pindex);  in radeon_setcolreg()
1102 			OUTREG(PALETTE_DATA, (red << 16) |  in radeon_setcolreg()
1146 			OUTREG(DAC_CNTL2, dac_cntl2);  in radeonfb_setcolreg()
1176 			OUTREG(DAC_CNTL2, dac_cntl2);  in radeonfb_setcmap()
1346 	OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);  in radeon_lvds_timer_func()
1367 		OUTREG(common_regs[i].reg, common_regs[i].val);  in radeon_write_mode()
1371 		OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);  in radeon_write_mode()
1372 		OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);  in radeon_write_mode()
1373 		OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);  in radeon_write_mode()
1376 	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);  in radeon_write_mode()
1379 	OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);  in radeon_write_mode()
1381 	OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);  in radeon_write_mode()
1382 	OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);  in radeon_write_mode()
1383 	OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);  in radeon_write_mode()
1384 	OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);  in radeon_write_mode()
1385 	OUTREG(CRTC_OFFSET, 0);  in radeon_write_mode()
1386 	OUTREG(CRTC_OFFSET_CNTL, 0);  in radeon_write_mode()
1387 	OUTREG(CRTC_PITCH, mode->crtc_pitch);  in radeon_write_mode()
1388 	OUTREG(SURFACE_CNTL, mode->surface_cntl);  in radeon_write_mode()
1394 		OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);  in radeon_write_mode()
1395 		OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);  in radeon_write_mode()
1396 		OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);  in radeon_write_mode()
1397 		OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);  in radeon_write_mode()
1398 		OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);  in radeon_write_mode()
1399 		OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);  in radeon_write_mode()
1400 		OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);  in radeon_write_mode()
1401 		OUTREG(TMDS_CRC, mode->tmds_crc);  in radeon_write_mode()
1402 		OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);  in radeon_write_mode()
1930 		OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);  in fixup_memory_mappings()
1935 	OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);  in fixup_memory_mappings()
1936 	OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);  in fixup_memory_mappings()
1944 	OUTREG(MC_FB_LOCATION,   in fixup_memory_mappings()
1948 	OUTREG(MC_FB_LOCATION, 0x7fff0000);  in fixup_memory_mappings()
1960 	OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));  in fixup_memory_mappings()
1962 	OUTREG(MC_AGP_LOCATION, 0xffffe000);  in fixup_memory_mappings()
1969 	OUTREG(DISPLAY_BASE_ADDR, aper_base);  in fixup_memory_mappings()
1971 		OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);  in fixup_memory_mappings()
1972 	OUTREG(OV0_BASE_ADDR, aper_base);  in fixup_memory_mappings()
1974 	OUTREG(DISPLAY_BASE_ADDR, 0);  in fixup_memory_mappings()
1976 		OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);  in fixup_memory_mappings()
1977 	OUTREG(OV0_BASE_ADDR, 0);  in fixup_memory_mappings()
1982 	OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);  in fixup_memory_mappings()
1983 	OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);  in fixup_memory_mappings()
1985 		OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);	  in fixup_memory_mappings()
2010           OUTREG(MC_FB_LOCATION, tom);  in radeon_identify_vram()
2011           OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);  in radeon_identify_vram()
2012           OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);  in radeon_identify_vram()
2013           OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);  in radeon_identify_vram()
2016           OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);  in radeon_identify_vram()