189 #define SER_RXD_MASK         IO_MASK(R_SERIAL0_STATUS, rxd)
190 #define SER_DATA_AVAIL_MASK  IO_MASK(R_SERIAL0_STATUS, data_avail)
191 #define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
192 #define SER_PAR_ERR_MASK     IO_MASK(R_SERIAL0_STATUS, par_err)
193 #define SER_OVERRUN_MASK     IO_MASK(R_SERIAL0_STATUS, overrun)
219 | IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
222 | IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
225 | IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
228 | IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
1146 		(info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));  in e100_disable_rx()
1156 		(info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));  in e100_enable_rx()
1212 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==  in e100_disable_txdma_channel()
1214 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma6);  in e100_disable_txdma_channel()
1218 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==  in e100_disable_txdma_channel()
1220 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma8);  in e100_disable_txdma_channel()
1224 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==  in e100_disable_txdma_channel()
1226 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma2);  in e100_disable_txdma_channel()
1230 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==  in e100_disable_txdma_channel()
1232 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma4);  in e100_disable_txdma_channel()
1249 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma6);  in e100_enable_txdma_channel()
1252 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma8);  in e100_enable_txdma_channel()
1255 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma2);  in e100_enable_txdma_channel()
1258 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma4);  in e100_enable_txdma_channel()
1274 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==  in e100_disable_rxdma_channel()
1276 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma7);  in e100_disable_rxdma_channel()
1280 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==  in e100_disable_rxdma_channel()
1282 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma9);  in e100_disable_rxdma_channel()
1286 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==  in e100_disable_rxdma_channel()
1288 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma3);  in e100_disable_rxdma_channel()
1292 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==  in e100_disable_rxdma_channel()
1294 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma5);  in e100_disable_rxdma_channel()
1310 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma7);  in e100_enable_rxdma_channel()
1313 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma9);  in e100_enable_rxdma_channel()
1316 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma3);  in e100_enable_rxdma_channel()
1319 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma5);  in e100_enable_rxdma_channel()
1892 	if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {  in receive_chars_dma()
2301 	if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {  in handle_ser_rx_interrupt_no_dma()
2306 	if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |  in handle_ser_rx_interrupt_no_dma()
2307 			  IO_MASK(R_SERIAL0_READ, par_err) |  in handle_ser_rx_interrupt_no_dma()
2308 			  IO_MASK(R_SERIAL0_READ, overrun) )) {  in handle_ser_rx_interrupt_no_dma()
2321 		if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&  in handle_ser_rx_interrupt_no_dma()
2322 		     (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {  in handle_ser_rx_interrupt_no_dma()
2330 			if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {  in handle_ser_rx_interrupt_no_dma()
2359 				if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {  in handle_ser_rx_interrupt_no_dma()
2362 				} else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {  in handle_ser_rx_interrupt_no_dma()
2365 				} else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {  in handle_ser_rx_interrupt_no_dma()
2374 	} else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {  in handle_ser_rx_interrupt_no_dma()
2395 	if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {  in handle_ser_rx_interrupt_no_dma()
2417 	if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {  in handle_ser_rx_interrupt()
2659 		irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |  in ser_interrupt()
2660 				 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |  in ser_interrupt()
2661 				 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |  in ser_interrupt()
2662 				 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));  in ser_interrupt()
2690 		ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |  in ser_interrupt()
2691 					     IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |  in ser_interrupt()
2692 					     IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |  in ser_interrupt()
2693 					     IO_MASK(R_IRQ_MASK1_RD, ser3_ready));  in ser_interrupt()
3048 	info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |  in change_speed()
3049 			   IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |  in change_speed()
3050 			   IO_MASK(R_SERIAL0_REC_CTRL, rec_par));  in change_speed()
3053 	info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |  in change_speed()
3054 			   IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |  in change_speed()
3055 			   IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |  in change_speed()
3056 			   IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |  in change_speed()
3057 			   IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));  in change_speed()
4306 		if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))  in seq_line_info()